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https://github.com/c64scene-ar/llvm-6502.git
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Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
382 lines
13 KiB
LLVM
382 lines
13 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s
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; CHECK-LABEL: test256_1
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; CHECK: vpcmpeqq {{.*%k[0-7]}}
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; CHECK: vmovdqa64 {{.*}}%k1
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; CHECK: ret
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define <4 x i64> @test256_1(<4 x i64> %x, <4 x i64> %y) nounwind {
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%mask = icmp eq <4 x i64> %x, %y
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%max = select <4 x i1> %mask, <4 x i64> %x, <4 x i64> %y
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ret <4 x i64> %max
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}
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; CHECK-LABEL: test256_2
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; CHECK: vpcmpgtq {{.*%k[0-7]}}
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; CHECK: vmovdqa64 {{.*}}%k1
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; CHECK: ret
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define <4 x i64> @test256_2(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1) nounwind {
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%mask = icmp sgt <4 x i64> %x, %y
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%max = select <4 x i1> %mask, <4 x i64> %x1, <4 x i64> %y
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ret <4 x i64> %max
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}
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; CHECK-LABEL: @test256_3
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; CHECK: vpcmpled {{.*%k[0-7]}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <8 x i32> @test256_3(<8 x i32> %x, <8 x i32> %y, <8 x i32> %x1) nounwind {
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%mask = icmp sge <8 x i32> %x, %y
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%max = select <8 x i1> %mask, <8 x i32> %x1, <8 x i32> %y
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ret <8 x i32> %max
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}
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; CHECK-LABEL: test256_4
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; CHECK: vpcmpnleuq {{.*%k[0-7]}}
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; CHECK: vmovdqa64 {{.*}}%k1
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; CHECK: ret
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define <4 x i64> @test256_4(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1) nounwind {
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%mask = icmp ugt <4 x i64> %x, %y
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%max = select <4 x i1> %mask, <4 x i64> %x1, <4 x i64> %y
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ret <4 x i64> %max
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}
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; CHECK-LABEL: test256_5
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; CHECK: vpcmpeqd (%rdi){{.*%k[0-7]}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <8 x i32> @test256_5(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %yp) nounwind {
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%y = load <8 x i32>, <8 x i32>* %yp, align 4
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%mask = icmp eq <8 x i32> %x, %y
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%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %x1
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ret <8 x i32> %max
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}
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; CHECK-LABEL: @test256_6
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; CHECK: vpcmpgtd (%rdi){{.*%k[0-7]}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <8 x i32> @test256_6(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) nounwind {
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%y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
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%mask = icmp sgt <8 x i32> %x, %y
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%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %x1
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ret <8 x i32> %max
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}
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; CHECK-LABEL: @test256_7
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; CHECK: vpcmpled (%rdi){{.*%k[0-7]}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <8 x i32> @test256_7(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) nounwind {
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%y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
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%mask = icmp sle <8 x i32> %x, %y
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%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %x1
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ret <8 x i32> %max
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}
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; CHECK-LABEL: @test256_8
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; CHECK: vpcmpleud (%rdi){{.*%k[0-7]}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <8 x i32> @test256_8(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) nounwind {
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%y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
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%mask = icmp ule <8 x i32> %x, %y
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%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %x1
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ret <8 x i32> %max
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}
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; CHECK-LABEL: @test256_9
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; CHECK: vpcmpeqd %ymm{{.*{%k[1-7]}}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <8 x i32> @test256_9(<8 x i32> %x, <8 x i32> %y, <8 x i32> %x1, <8 x i32> %y1) nounwind {
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%mask1 = icmp eq <8 x i32> %x1, %y1
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%mask0 = icmp eq <8 x i32> %x, %y
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%mask = select <8 x i1> %mask0, <8 x i1> %mask1, <8 x i1> zeroinitializer
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%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
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ret <8 x i32> %max
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}
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; CHECK-LABEL: @test256_10
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; CHECK: vpcmpleq %ymm{{.*{%k[1-7]}}}
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; CHECK: vmovdqa64
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; CHECK: ret
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define <4 x i64> @test256_10(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1, <4 x i64> %y1) nounwind {
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%mask1 = icmp sge <4 x i64> %x1, %y1
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%mask0 = icmp sle <4 x i64> %x, %y
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%mask = select <4 x i1> %mask0, <4 x i1> %mask1, <4 x i1> zeroinitializer
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%max = select <4 x i1> %mask, <4 x i64> %x, <4 x i64> %x1
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ret <4 x i64> %max
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}
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; CHECK-LABEL: @test256_11
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; CHECK: vpcmpgtq (%rdi){{.*{%k[1-7]}}}
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; CHECK: vmovdqa64
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; CHECK: ret
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define <4 x i64> @test256_11(<4 x i64> %x, <4 x i64>* %y.ptr, <4 x i64> %x1, <4 x i64> %y1) nounwind {
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%mask1 = icmp sgt <4 x i64> %x1, %y1
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%y = load <4 x i64>, <4 x i64>* %y.ptr, align 4
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%mask0 = icmp sgt <4 x i64> %x, %y
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%mask = select <4 x i1> %mask0, <4 x i1> %mask1, <4 x i1> zeroinitializer
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%max = select <4 x i1> %mask, <4 x i64> %x, <4 x i64> %x1
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ret <4 x i64> %max
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}
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; CHECK-LABEL: @test256_12
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; CHECK: vpcmpleud (%rdi){{.*{%k[1-7]}}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <8 x i32> @test256_12(<8 x i32> %x, <8 x i32>* %y.ptr, <8 x i32> %x1, <8 x i32> %y1) nounwind {
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%mask1 = icmp sge <8 x i32> %x1, %y1
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%y = load <8 x i32>, <8 x i32>* %y.ptr, align 4
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%mask0 = icmp ule <8 x i32> %x, %y
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%mask = select <8 x i1> %mask0, <8 x i1> %mask1, <8 x i1> zeroinitializer
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%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %x1
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ret <8 x i32> %max
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}
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; CHECK-LABEL: test256_13
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; CHECK: vpcmpeqq (%rdi){1to4}, %ymm
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; CHECK: vmovdqa64
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; CHECK: ret
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define <4 x i64> @test256_13(<4 x i64> %x, <4 x i64> %x1, i64* %yb.ptr) nounwind {
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%yb = load i64, i64* %yb.ptr, align 4
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%y.0 = insertelement <4 x i64> undef, i64 %yb, i32 0
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%y = shufflevector <4 x i64> %y.0, <4 x i64> undef, <4 x i32> zeroinitializer
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%mask = icmp eq <4 x i64> %x, %y
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%max = select <4 x i1> %mask, <4 x i64> %x, <4 x i64> %x1
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ret <4 x i64> %max
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}
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; CHECK-LABEL: test256_14
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; CHECK: vpcmpled (%rdi){1to8}, %ymm
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; CHECK: vmovdqa32
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; CHECK: ret
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define <8 x i32> @test256_14(<8 x i32> %x, i32* %yb.ptr, <8 x i32> %x1) nounwind {
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%yb = load i32, i32* %yb.ptr, align 4
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%y.0 = insertelement <8 x i32> undef, i32 %yb, i32 0
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%y = shufflevector <8 x i32> %y.0, <8 x i32> undef, <8 x i32> zeroinitializer
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%mask = icmp sle <8 x i32> %x, %y
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%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %x1
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ret <8 x i32> %max
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}
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; CHECK-LABEL: test256_15
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; CHECK: vpcmpgtd (%rdi){1to8}, %ymm{{.*{%k[1-7]}}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <8 x i32> @test256_15(<8 x i32> %x, i32* %yb.ptr, <8 x i32> %x1, <8 x i32> %y1) nounwind {
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%mask1 = icmp sge <8 x i32> %x1, %y1
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%yb = load i32, i32* %yb.ptr, align 4
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%y.0 = insertelement <8 x i32> undef, i32 %yb, i32 0
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%y = shufflevector <8 x i32> %y.0, <8 x i32> undef, <8 x i32> zeroinitializer
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%mask0 = icmp sgt <8 x i32> %x, %y
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%mask = select <8 x i1> %mask0, <8 x i1> %mask1, <8 x i1> zeroinitializer
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%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %x1
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ret <8 x i32> %max
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}
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; CHECK-LABEL: test256_16
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; CHECK: vpcmpgtq (%rdi){1to4}, %ymm{{.*{%k[1-7]}}}
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; CHECK: vmovdqa64
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; CHECK: ret
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define <4 x i64> @test256_16(<4 x i64> %x, i64* %yb.ptr, <4 x i64> %x1, <4 x i64> %y1) nounwind {
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%mask1 = icmp sge <4 x i64> %x1, %y1
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%yb = load i64, i64* %yb.ptr, align 4
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%y.0 = insertelement <4 x i64> undef, i64 %yb, i32 0
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%y = shufflevector <4 x i64> %y.0, <4 x i64> undef, <4 x i32> zeroinitializer
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%mask0 = icmp sgt <4 x i64> %x, %y
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%mask = select <4 x i1> %mask0, <4 x i1> %mask1, <4 x i1> zeroinitializer
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%max = select <4 x i1> %mask, <4 x i64> %x, <4 x i64> %x1
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ret <4 x i64> %max
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}
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; CHECK-LABEL: test128_1
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; CHECK: vpcmpeqq {{.*%k[0-7]}}
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; CHECK: vmovdqa64 {{.*}}%k1
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; CHECK: ret
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define <2 x i64> @test128_1(<2 x i64> %x, <2 x i64> %y) nounwind {
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%mask = icmp eq <2 x i64> %x, %y
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%max = select <2 x i1> %mask, <2 x i64> %x, <2 x i64> %y
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ret <2 x i64> %max
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}
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; CHECK-LABEL: test128_2
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; CHECK: vpcmpgtq {{.*%k[0-7]}}
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; CHECK: vmovdqa64 {{.*}}%k1
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; CHECK: ret
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define <2 x i64> @test128_2(<2 x i64> %x, <2 x i64> %y, <2 x i64> %x1) nounwind {
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%mask = icmp sgt <2 x i64> %x, %y
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%max = select <2 x i1> %mask, <2 x i64> %x1, <2 x i64> %y
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ret <2 x i64> %max
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}
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; CHECK-LABEL: @test128_3
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; CHECK: vpcmpled {{.*%k[0-7]}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <4 x i32> @test128_3(<4 x i32> %x, <4 x i32> %y, <4 x i32> %x1) nounwind {
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%mask = icmp sge <4 x i32> %x, %y
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%max = select <4 x i1> %mask, <4 x i32> %x1, <4 x i32> %y
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ret <4 x i32> %max
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}
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; CHECK-LABEL: test128_4
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; CHECK: vpcmpnleuq {{.*%k[0-7]}}
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; CHECK: vmovdqa64 {{.*}}%k1
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; CHECK: ret
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define <2 x i64> @test128_4(<2 x i64> %x, <2 x i64> %y, <2 x i64> %x1) nounwind {
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%mask = icmp ugt <2 x i64> %x, %y
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%max = select <2 x i1> %mask, <2 x i64> %x1, <2 x i64> %y
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ret <2 x i64> %max
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}
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; CHECK-LABEL: test128_5
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; CHECK: vpcmpeqd (%rdi){{.*%k[0-7]}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <4 x i32> @test128_5(<4 x i32> %x, <4 x i32> %x1, <4 x i32>* %yp) nounwind {
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%y = load <4 x i32>, <4 x i32>* %yp, align 4
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%mask = icmp eq <4 x i32> %x, %y
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%max = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %x1
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ret <4 x i32> %max
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}
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; CHECK-LABEL: @test128_6
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; CHECK: vpcmpgtd (%rdi){{.*%k[0-7]}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <4 x i32> @test128_6(<4 x i32> %x, <4 x i32> %x1, <4 x i32>* %y.ptr) nounwind {
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%y = load <4 x i32>, <4 x i32>* %y.ptr, align 4
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%mask = icmp sgt <4 x i32> %x, %y
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%max = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %x1
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ret <4 x i32> %max
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}
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; CHECK-LABEL: @test128_7
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; CHECK: vpcmpled (%rdi){{.*%k[0-7]}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <4 x i32> @test128_7(<4 x i32> %x, <4 x i32> %x1, <4 x i32>* %y.ptr) nounwind {
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%y = load <4 x i32>, <4 x i32>* %y.ptr, align 4
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%mask = icmp sle <4 x i32> %x, %y
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%max = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %x1
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ret <4 x i32> %max
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}
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; CHECK-LABEL: @test128_8
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; CHECK: vpcmpleud (%rdi){{.*%k[0-7]}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <4 x i32> @test128_8(<4 x i32> %x, <4 x i32> %x1, <4 x i32>* %y.ptr) nounwind {
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%y = load <4 x i32>, <4 x i32>* %y.ptr, align 4
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%mask = icmp ule <4 x i32> %x, %y
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%max = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %x1
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ret <4 x i32> %max
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}
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; CHECK-LABEL: @test128_9
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; CHECK: vpcmpeqd %xmm{{.*{%k[1-7]}}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <4 x i32> @test128_9(<4 x i32> %x, <4 x i32> %y, <4 x i32> %x1, <4 x i32> %y1) nounwind {
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%mask1 = icmp eq <4 x i32> %x1, %y1
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%mask0 = icmp eq <4 x i32> %x, %y
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%mask = select <4 x i1> %mask0, <4 x i1> %mask1, <4 x i1> zeroinitializer
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%max = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %max
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}
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; CHECK-LABEL: @test128_10
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; CHECK: vpcmpleq %xmm{{.*{%k[1-7]}}}
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; CHECK: vmovdqa64
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; CHECK: ret
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define <2 x i64> @test128_10(<2 x i64> %x, <2 x i64> %y, <2 x i64> %x1, <2 x i64> %y1) nounwind {
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%mask1 = icmp sge <2 x i64> %x1, %y1
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%mask0 = icmp sle <2 x i64> %x, %y
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%mask = select <2 x i1> %mask0, <2 x i1> %mask1, <2 x i1> zeroinitializer
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%max = select <2 x i1> %mask, <2 x i64> %x, <2 x i64> %x1
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ret <2 x i64> %max
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}
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; CHECK-LABEL: @test128_11
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; CHECK: vpcmpgtq (%rdi){{.*{%k[1-7]}}}
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; CHECK: vmovdqa64
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; CHECK: ret
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define <2 x i64> @test128_11(<2 x i64> %x, <2 x i64>* %y.ptr, <2 x i64> %x1, <2 x i64> %y1) nounwind {
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%mask1 = icmp sgt <2 x i64> %x1, %y1
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%y = load <2 x i64>, <2 x i64>* %y.ptr, align 4
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%mask0 = icmp sgt <2 x i64> %x, %y
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%mask = select <2 x i1> %mask0, <2 x i1> %mask1, <2 x i1> zeroinitializer
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%max = select <2 x i1> %mask, <2 x i64> %x, <2 x i64> %x1
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ret <2 x i64> %max
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}
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; CHECK-LABEL: @test128_12
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; CHECK: vpcmpleud (%rdi){{.*{%k[1-7]}}}
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; CHECK: vmovdqa32
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; CHECK: ret
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define <4 x i32> @test128_12(<4 x i32> %x, <4 x i32>* %y.ptr, <4 x i32> %x1, <4 x i32> %y1) nounwind {
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%mask1 = icmp sge <4 x i32> %x1, %y1
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%y = load <4 x i32>, <4 x i32>* %y.ptr, align 4
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%mask0 = icmp ule <4 x i32> %x, %y
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%mask = select <4 x i1> %mask0, <4 x i1> %mask1, <4 x i1> zeroinitializer
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%max = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %x1
|
|
ret <4 x i32> %max
|
|
}
|
|
|
|
; CHECK-LABEL: test128_13
|
|
; CHECK: vpcmpeqq (%rdi){1to2}, %xmm
|
|
; CHECK: vmovdqa64
|
|
; CHECK: ret
|
|
define <2 x i64> @test128_13(<2 x i64> %x, <2 x i64> %x1, i64* %yb.ptr) nounwind {
|
|
%yb = load i64, i64* %yb.ptr, align 4
|
|
%y.0 = insertelement <2 x i64> undef, i64 %yb, i32 0
|
|
%y = insertelement <2 x i64> %y.0, i64 %yb, i32 1
|
|
%mask = icmp eq <2 x i64> %x, %y
|
|
%max = select <2 x i1> %mask, <2 x i64> %x, <2 x i64> %x1
|
|
ret <2 x i64> %max
|
|
}
|
|
|
|
; CHECK-LABEL: test128_14
|
|
; CHECK: vpcmpled (%rdi){1to4}, %xmm
|
|
; CHECK: vmovdqa32
|
|
; CHECK: ret
|
|
define <4 x i32> @test128_14(<4 x i32> %x, i32* %yb.ptr, <4 x i32> %x1) nounwind {
|
|
%yb = load i32, i32* %yb.ptr, align 4
|
|
%y.0 = insertelement <4 x i32> undef, i32 %yb, i32 0
|
|
%y = shufflevector <4 x i32> %y.0, <4 x i32> undef, <4 x i32> zeroinitializer
|
|
%mask = icmp sle <4 x i32> %x, %y
|
|
%max = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %x1
|
|
ret <4 x i32> %max
|
|
}
|
|
|
|
; CHECK-LABEL: test128_15
|
|
; CHECK: vpcmpgtd (%rdi){1to4}, %xmm{{.*{%k[1-7]}}}
|
|
; CHECK: vmovdqa32
|
|
; CHECK: ret
|
|
define <4 x i32> @test128_15(<4 x i32> %x, i32* %yb.ptr, <4 x i32> %x1, <4 x i32> %y1) nounwind {
|
|
%mask1 = icmp sge <4 x i32> %x1, %y1
|
|
%yb = load i32, i32* %yb.ptr, align 4
|
|
%y.0 = insertelement <4 x i32> undef, i32 %yb, i32 0
|
|
%y = shufflevector <4 x i32> %y.0, <4 x i32> undef, <4 x i32> zeroinitializer
|
|
%mask0 = icmp sgt <4 x i32> %x, %y
|
|
%mask = select <4 x i1> %mask0, <4 x i1> %mask1, <4 x i1> zeroinitializer
|
|
%max = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %x1
|
|
ret <4 x i32> %max
|
|
}
|
|
|
|
; CHECK-LABEL: test128_16
|
|
; CHECK: vpcmpgtq (%rdi){1to2}, %xmm{{.*{%k[1-7]}}}
|
|
; CHECK: vmovdqa64
|
|
; CHECK: ret
|
|
define <2 x i64> @test128_16(<2 x i64> %x, i64* %yb.ptr, <2 x i64> %x1, <2 x i64> %y1) nounwind {
|
|
%mask1 = icmp sge <2 x i64> %x1, %y1
|
|
%yb = load i64, i64* %yb.ptr, align 4
|
|
%y.0 = insertelement <2 x i64> undef, i64 %yb, i32 0
|
|
%y = insertelement <2 x i64> %y.0, i64 %yb, i32 1
|
|
%mask0 = icmp sgt <2 x i64> %x, %y
|
|
%mask = select <2 x i1> %mask0, <2 x i1> %mask1, <2 x i1> zeroinitializer
|
|
%max = select <2 x i1> %mask, <2 x i64> %x, <2 x i64> %x1
|
|
ret <2 x i64> %max
|
|
}
|