mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 17:29:19 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121355 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
1.4 KiB
Plaintext
27 lines
1.4 KiB
Plaintext
* Writing out ELF files is close to working but the following needs to
|
|
be examined more closely:
|
|
- Relocations use 2-byte / 4-byte to terminology in reference to
|
|
the size of the immediate value being changed. The Xilinx
|
|
terminology seems to be (???) 4-byte / 8-byte in reference
|
|
to the number of bytes of instructions that are being changed.
|
|
|
|
* Code generation seems to work relatively well now but the following
|
|
needs to be examined more closely:
|
|
- The stack layout needs to be examined to make sure it meets
|
|
the standard, especially in regards to var arg functions.
|
|
- The processor itineraries are copied from a different backend
|
|
and need to be updated to model the MicroBlaze correctly.
|
|
- Look at the MBlazeGenFastISel.inc stuff and make use of it
|
|
if appropriate.
|
|
|
|
* A basic assembly parser is present now and seems to parse most things.
|
|
There are a few things that need to be looked at:
|
|
- There are some instructions that are not generated by the backend
|
|
and have not been tested as far as the parser is concerned.
|
|
- The assembly parser does not use any MicroBlaze specific directives.
|
|
I should investigate if there are MicroBlaze specific directive and,
|
|
if there are, add them.
|
|
- The instruction MFS and MTS use special names for some of the
|
|
special registers that can be accessed. These special register
|
|
names should be parsed by the assembly parser.
|