Jack Carter e035f65b16 Doubleword Shift Left Logical Plus 32 ... Mips shift instructions DSLL, DSRL and DSRA are transformed into DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between 32 and 63 Here is a description of DSLL: Purpose: Doubleword Shift Left Logical Plus 32 To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits Description: GPR[rd] <- GPR[rt] << (sa+32) The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the emptied bits; the result is placed in GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa. This patch implements the direct object output of these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8		2012-07-16 15:14:51 +00:00
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ARM	Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!	2012-07-10 12:51:09 +00:00
AsmParser	Convert the uses of '|&' to use '2>&1 |' instead, which works on old	2012-07-02 18:37:59 +00:00
COFF	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
Disassembler	Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck.	2012-07-12 21:19:32 +00:00
ELF	ELF: Add support for the asm .version directive.	2012-05-12 14:30:47 +00:00
MachO	Refactor data-in-code annotations.	2012-05-18 19:12:01 +00:00
MBlaze	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
Mips	Doubleword Shift Left Logical Plus 32	2012-07-16 15:14:51 +00:00
X86	Reverse assembler/disassembler operand order for gather instructions.	2012-07-10 06:38:33 +00:00