llvm-6502/lib/Target/Sparc
Chandler Carruth d04a8d4b33 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 16:50:05 +00:00
..
MCTargetDesc
TargetInfo
CMakeLists.txt
DelaySlotFiller.cpp Use the new script to sort the includes of every file under lib. 2012-12-03 16:50:05 +00:00
FPMover.cpp Use the new script to sort the includes of every file under lib. 2012-12-03 16:50:05 +00:00
LLVMBuild.txt
Makefile
README.txt
Sparc.h
Sparc.td
SparcAsmPrinter.cpp Use the new script to sort the includes of every file under lib. 2012-12-03 16:50:05 +00:00
SparcCallingConv.td
SparcFrameLowering.cpp Use the new script to sort the includes of every file under lib. 2012-12-03 16:50:05 +00:00
SparcFrameLowering.h
SparcInstrFormats.td
SparcInstrInfo.cpp Use the new script to sort the includes of every file under lib. 2012-12-03 16:50:05 +00:00
SparcInstrInfo.h
SparcInstrInfo.td
SparcISelDAGToDAG.cpp Use the new script to sort the includes of every file under lib. 2012-12-03 16:50:05 +00:00
SparcISelLowering.cpp Use the new script to sort the includes of every file under lib. 2012-12-03 16:50:05 +00:00
SparcISelLowering.h
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcRegisterInfo.cpp Use the new script to sort the includes of every file under lib. 2012-12-03 16:50:05 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetMachine.cpp Use the new script to sort the includes of every file under lib. 2012-12-03 16:50:05 +00:00
SparcTargetMachine.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support