llvm-6502/test/CodeGen/X86/fast-isel-x86.ll
Andrew Trick 922d314e8f Instruction scheduling itinerary for Intel Atom.
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01 23:20:51 +00:00

49 lines
1.1 KiB
LLVM

; RUN: llc -fast-isel -O0 -mcpu=generic -mtriple=i386-apple-darwin10 -relocation-model=pic < %s | FileCheck %s
; This should use flds to set the return value.
; CHECK: test0:
; CHECK: flds
; CHECK: ret
@G = external global float
define float @test0() nounwind {
%t = load float* @G
ret float %t
}
; This should pop 4 bytes on return.
; CHECK: test1:
; CHECK: ret $4
define void @test1({i32, i32, i32, i32}* sret %p) nounwind {
store {i32, i32, i32, i32} zeroinitializer, {i32, i32, i32, i32}* %p
ret void
}
; Properly initialize the pic base.
; CHECK: test2:
; CHECK-NOT: HHH
; CHECK: call{{.*}}L2$pb
; CHECK-NEXT: L2$pb:
; CHECK-NEXT: pop
; CHECK: HHH
; CHECK: ret
@HHH = external global i32
define i32 @test2() nounwind {
%t = load i32* @HHH
ret i32 %t
}
; Check that we fast-isel sret, and handle the callee-pops behavior correctly.
%struct.a = type { i64, i64, i64 }
define void @test3() nounwind ssp {
entry:
%tmp = alloca %struct.a, align 8
call void @test3sret(%struct.a* sret %tmp)
ret void
; CHECK: test3:
; CHECK: subl $44
; CHECK: leal 16(%esp)
; CHECK: calll _test3sret
; CHECK: addl $40
}
declare void @test3sret(%struct.a* sret)