Andrea Di Biagio 19e39c6f12 [DAGCombiner] Improve the shuffle-vector folding logic. ... Canonicalize shuffles according to rules: * shuffle(A, shuffle(A, B)) -> shuffle(shuffle(A,B), A) * shuffle(B, shuffle(A, B)) -> shuffle(shuffle(A,B), B) * shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B) This patch helps identifying more shuffle pairs that could be combined reusing the already existing rules in the DAGCombiner. Added new test 'combine-vec-shuffle-5.ll' to verify that the canonicalized shuffles are now folded into a single shuffle node by the DAGCombiner. Added more test cases to 'combine-vec-shuffle-4.ll'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213504 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-21 07:30:54 +00:00
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AArch64	AArch64: implement efficient f16 bitcasts	2014-07-18 13:07:05 +00:00
ARM	ARM: correct WoA __builtin_alloca handling on O0	2014-07-19 01:29:51 +00:00
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Mips	[mips] For the FP64A ABI, odd-numbered double-precision moves must not use mtc1/mfc1.	2014-07-14 13:08:14 +00:00
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NVPTX	Add tests for atomic adds on floats.	2014-07-18 20:11:26 +00:00
PowerPC	[PowerPC] ELFv2 aggregate passing support	2014-07-21 00:13:26 +00:00
R600	R600: Add missing test for concat_vectors	2014-07-20 07:13:17 +00:00
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X86	[DAGCombiner] Improve the shuffle-vector folding logic.	2014-07-21 07:30:54 +00:00
XCore