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d4cdf88cb9
-Wunused-but-set-variable. Leftover from r181979. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181993 91177308-0d34-0410-b5e6-96231b3b80d8
389 lines
14 KiB
C++
389 lines
14 KiB
C++
//===-- XCoreFrameLowering.cpp - Frame info for XCore Target --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains XCore frame information that doesn't fit anywhere else
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// cleanly...
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//
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//===----------------------------------------------------------------------===//
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#include "XCoreFrameLowering.h"
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#include "XCore.h"
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#include "XCoreInstrInfo.h"
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#include "XCoreMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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// helper functions. FIXME: Eliminate.
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static inline bool isImmUs(unsigned val) {
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return val <= 11;
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}
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static inline bool isImmU6(unsigned val) {
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return val < (1 << 6);
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}
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static inline bool isImmU16(unsigned val) {
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return val < (1 << 16);
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}
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static void loadFromStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, int Offset, DebugLoc dl,
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const TargetInstrInfo &TII) {
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assert(Offset%4 == 0 && "Misaligned stack offset");
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Offset/=4;
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bool isU6 = isImmU6(Offset);
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if (!isU6 && !isImmU16(Offset))
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report_fatal_error("loadFromStack offset too big " + Twine(Offset));
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int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
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BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
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.addImm(Offset);
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}
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static void storeToStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned SrcReg, int Offset, DebugLoc dl,
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const TargetInstrInfo &TII) {
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assert(Offset%4 == 0 && "Misaligned stack offset");
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Offset/=4;
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bool isU6 = isImmU6(Offset);
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if (!isU6 && !isImmU16(Offset))
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report_fatal_error("storeToStack offset too big " + Twine(Offset));
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int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
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BuildMI(MBB, I, dl, TII.get(Opcode))
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.addReg(SrcReg)
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.addImm(Offset);
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}
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//===----------------------------------------------------------------------===//
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// XCoreFrameLowering:
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//===----------------------------------------------------------------------===//
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XCoreFrameLowering::XCoreFrameLowering(const XCoreSubtarget &sti)
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0) {
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// Do nothing
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}
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bool XCoreFrameLowering::hasFP(const MachineFunction &MF) const {
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return MF.getTarget().Options.DisableFramePointerElim(MF) ||
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MF.getFrameInfo()->hasVarSizedObjects();
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}
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void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineModuleInfo *MMI = &MF.getMMI();
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const XCoreInstrInfo &TII =
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*static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
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XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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bool FP = hasFP(MF);
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const AttributeSet &PAL = MF.getFunction()->getAttributes();
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if (PAL.hasAttrSomewhere(Attribute::Nest))
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loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII);
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// Work out frame sizes.
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int FrameSize = MFI->getStackSize();
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assert(FrameSize%4 == 0 && "Misaligned frame size");
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FrameSize/=4;
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bool isU6 = isImmU6(FrameSize);
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if (!isU6 && !isImmU16(FrameSize)) {
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// FIXME could emit multiple instructions.
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report_fatal_error("emitPrologue Frame size too big: " + Twine(FrameSize));
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}
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bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(MF);
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bool saveLR = XFI->getUsesLR();
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// Do we need to allocate space on the stack?
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if (FrameSize) {
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int Opcode;
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if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) {
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Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
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MBB.addLiveIn(XCore::LR);
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saveLR = false;
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} else {
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Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
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}
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BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
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if (emitFrameMoves) {
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// Show update of SP.
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MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
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}
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}
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if (saveLR) {
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int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
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storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII);
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MBB.addLiveIn(XCore::LR);
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if (emitFrameMoves) {
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MCSymbol *SaveLRLabel = MMI->getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel);
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}
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}
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if (FP) {
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// Save R10 to the stack.
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int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
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storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl, TII);
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// R10 is live-in. It is killed at the spill.
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MBB.addLiveIn(XCore::R10);
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if (emitFrameMoves) {
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MCSymbol *SaveR10Label = MMI->getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label);
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}
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// Set the FP from the SP.
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unsigned FramePtr = XCore::R10;
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BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
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.addImm(0);
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if (emitFrameMoves) {
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// Show FP is now valid.
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MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
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}
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}
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}
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void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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const XCoreInstrInfo &TII =
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*static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
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XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
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DebugLoc dl = MBBI->getDebugLoc();
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bool FP = hasFP(MF);
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if (FP) {
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// Restore the stack pointer.
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unsigned FramePtr = XCore::R10;
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BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
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.addReg(FramePtr);
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}
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// Work out frame sizes.
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int FrameSize = MFI->getStackSize();
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assert(FrameSize%4 == 0 && "Misaligned frame size");
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FrameSize/=4;
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bool isU6 = isImmU6(FrameSize);
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if (!isU6 && !isImmU16(FrameSize)) {
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// FIXME could emit multiple instructions.
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report_fatal_error("emitEpilogue Frame size too big: " + Twine(FrameSize));
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}
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if (FP) {
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// Restore R10
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int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
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FPSpillOffset += FrameSize*4;
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loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl, TII);
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}
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bool restoreLR = XFI->getUsesLR();
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if (restoreLR &&
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(FrameSize == 0 || MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0)) {
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int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
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LRSpillOffset += FrameSize*4;
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loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl, TII);
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restoreLR = false;
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}
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if (FrameSize) {
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if (restoreLR) {
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// Fold prologue into return instruction
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assert(MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0);
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assert(MBBI->getOpcode() == XCore::RETSP_u6
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|| MBBI->getOpcode() == XCore::RETSP_lu6);
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int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
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MBB.erase(MBBI);
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} else {
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int Opcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
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}
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}
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}
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bool XCoreFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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if (CSI.empty())
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return true;
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MachineFunction *MF = MBB.getParent();
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const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
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XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>();
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bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
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it != CSI.end(); ++it) {
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// Add the callee-saved register as live-in. It's killed at the spill.
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MBB.addLiveIn(it->getReg());
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unsigned Reg = it->getReg();
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.storeRegToStackSlot(MBB, MI, Reg, true,
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it->getFrameIdx(), RC, TRI);
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if (emitFrameMoves) {
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MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol();
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BuildMI(MBB, MI, DL, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLabel);
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XFI->getSpillLabels().push_back(std::make_pair(SaveLabel, *it));
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}
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}
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return true;
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}
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bool XCoreFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const{
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MachineFunction *MF = MBB.getParent();
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const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
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bool AtStart = MI == MBB.begin();
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MachineBasicBlock::iterator BeforeI = MI;
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if (!AtStart)
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--BeforeI;
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for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
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it != CSI.end(); ++it) {
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unsigned Reg = it->getReg();
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.loadRegFromStackSlot(MBB, MI, it->getReg(), it->getFrameIdx(),
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RC, TRI);
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assert(MI != MBB.begin() &&
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"loadRegFromStackSlot didn't insert any code!");
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// Insert in reverse order. loadRegFromStackSlot can insert multiple
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// instructions.
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if (AtStart)
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MI = MBB.begin();
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else {
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MI = BeforeI;
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++MI;
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}
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}
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return true;
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}
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// This function eliminates ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP pseudo instructions
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void XCoreFrameLowering::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const XCoreInstrInfo &TII =
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*static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
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if (!hasReservedCallFrame(MF)) {
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// Turn the adjcallstackdown instruction into 'extsp <amt>' and the
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// adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
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MachineInstr *Old = I;
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uint64_t Amount = Old->getOperand(0).getImm();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned Align = getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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assert(Amount%4 == 0);
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Amount /= 4;
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bool isU6 = isImmU6(Amount);
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if (!isU6 && !isImmU16(Amount)) {
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// FIX could emit multiple instructions in this case.
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#ifndef NDEBUG
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errs() << "eliminateCallFramePseudoInstr size too big: "
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<< Amount << "\n";
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#endif
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llvm_unreachable(0);
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}
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MachineInstr *New;
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if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
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int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
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New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
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.addImm(Amount);
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} else {
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assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
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int Opcode = isU6 ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
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New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
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.addImm(Amount);
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}
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// Replace the pseudo instruction with a new instruction...
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MBB.insert(I, New);
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}
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}
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MBB.erase(I);
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}
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void
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XCoreFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
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bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
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const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
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XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
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if (LRUsed) {
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MF.getRegInfo().setPhysRegUnused(XCore::LR);
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bool isVarArg = MF.getFunction()->isVarArg();
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int FrameIdx;
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if (! isVarArg) {
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// A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
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FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true);
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} else {
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FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(),
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false);
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}
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XFI->setUsesLR(FrameIdx);
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XFI->setLRSpillSlot(FrameIdx);
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}
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if (RegInfo->requiresRegisterScavenging(MF)) {
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// Reserve a slot close to SP or frame pointer.
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RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
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RC->getAlignment(),
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false));
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}
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if (hasFP(MF)) {
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// A callee save register is used to hold the FP.
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// This needs saving / restoring in the epilogue / prologue.
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XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(),
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RC->getAlignment(),
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false));
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}
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}
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