mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-06 14:57:41 +00:00
04bcc11905
derived classes. Since global data alignment, layout, and mangling is often based on the DataLayout, move it to the TargetMachine. This ensures that global data is going to be layed out and mangled consistently if the subtarget changes on a per function basis. Prior to this all targets(*) have had subtarget dependent code moved out and onto the TargetMachine. *One target hasn't been migrated as part of this change: R600. The R600 port has, as a subtarget feature, the size of pointers and this affects global data layout. I've currently hacked in a FIXME to enable progress, but the port needs to be updated to either pass the 64-bitness to the TargetMachine, or fix the DataLayout to avoid subtarget dependent features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227113 91177308-0d34-0410-b5e6-96231b3b80d8
132 lines
4.9 KiB
C++
132 lines
4.9 KiB
C++
//===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file implements the AArch64 specific subclass of TargetSubtarget.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "AArch64InstrInfo.h"
|
|
#include "AArch64PBQPRegAlloc.h"
|
|
#include "AArch64Subtarget.h"
|
|
#include "llvm/ADT/SmallVector.h"
|
|
#include "llvm/CodeGen/MachineScheduler.h"
|
|
#include "llvm/IR/GlobalValue.h"
|
|
#include "llvm/Support/TargetRegistry.h"
|
|
|
|
using namespace llvm;
|
|
|
|
#define DEBUG_TYPE "aarch64-subtarget"
|
|
|
|
#define GET_SUBTARGETINFO_CTOR
|
|
#define GET_SUBTARGETINFO_TARGET_DESC
|
|
#include "AArch64GenSubtargetInfo.inc"
|
|
|
|
static cl::opt<bool>
|
|
EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
|
|
"converter pass"), cl::init(true), cl::Hidden);
|
|
|
|
AArch64Subtarget &
|
|
AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
|
|
// Determine default and user-specified characteristics
|
|
|
|
if (CPUString.empty())
|
|
CPUString = "generic";
|
|
|
|
ParseSubtargetFeatures(CPUString, FS);
|
|
return *this;
|
|
}
|
|
|
|
AArch64Subtarget::AArch64Subtarget(const std::string &TT,
|
|
const std::string &CPU,
|
|
const std::string &FS,
|
|
const TargetMachine &TM, bool LittleEndian)
|
|
: AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
|
|
HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false),
|
|
HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
|
|
IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
|
|
InstrInfo(initializeSubtargetDependencies(FS)),
|
|
TSInfo(TM.getDataLayout()), TLInfo(TM) {}
|
|
|
|
/// ClassifyGlobalReference - Find the target operand flags that describe
|
|
/// how a global value should be referenced for the current subtarget.
|
|
unsigned char
|
|
AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
|
|
const TargetMachine &TM) const {
|
|
bool isDecl = GV->isDeclarationForLinker();
|
|
|
|
// MachO large model always goes via a GOT, simply to get a single 8-byte
|
|
// absolute relocation on all global addresses.
|
|
if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
|
|
return AArch64II::MO_GOT;
|
|
|
|
// The small code mode's direct accesses use ADRP, which cannot necessarily
|
|
// produce the value 0 (if the code is above 4GB).
|
|
if (TM.getCodeModel() == CodeModel::Small &&
|
|
GV->isWeakForLinker() && isDecl) {
|
|
// In PIC mode use the GOT, but in absolute mode use a constant pool load.
|
|
if (TM.getRelocationModel() == Reloc::Static)
|
|
return AArch64II::MO_CONSTPOOL;
|
|
else
|
|
return AArch64II::MO_GOT;
|
|
}
|
|
|
|
// If symbol visibility is hidden, the extra load is not needed if
|
|
// the symbol is definitely defined in the current translation unit.
|
|
|
|
// The handling of non-hidden symbols in PIC mode is rather target-dependent:
|
|
// + On MachO, if the symbol is defined in this module the GOT can be
|
|
// skipped.
|
|
// + On ELF, the R_AARCH64_COPY relocation means that even symbols actually
|
|
// defined could end up in unexpected places. Use a GOT.
|
|
if (TM.getRelocationModel() != Reloc::Static && GV->hasDefaultVisibility()) {
|
|
if (isTargetMachO())
|
|
return (isDecl || GV->isWeakForLinker()) ? AArch64II::MO_GOT
|
|
: AArch64II::MO_NO_FLAG;
|
|
else
|
|
// No need to go through the GOT for local symbols on ELF.
|
|
return GV->hasLocalLinkage() ? AArch64II::MO_NO_FLAG : AArch64II::MO_GOT;
|
|
}
|
|
|
|
return AArch64II::MO_NO_FLAG;
|
|
}
|
|
|
|
/// This function returns the name of a function which has an interface
|
|
/// like the non-standard bzero function, if such a function exists on
|
|
/// the current subtarget and it is considered prefereable over
|
|
/// memset with zero passed as the second argument. Otherwise it
|
|
/// returns null.
|
|
const char *AArch64Subtarget::getBZeroEntry() const {
|
|
// Prefer bzero on Darwin only.
|
|
if(isTargetDarwin())
|
|
return "bzero";
|
|
|
|
return nullptr;
|
|
}
|
|
|
|
void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
|
|
MachineInstr *begin, MachineInstr *end,
|
|
unsigned NumRegionInstrs) const {
|
|
// LNT run (at least on Cyclone) showed reasonably significant gains for
|
|
// bi-directional scheduling. 253.perlbmk.
|
|
Policy.OnlyTopDown = false;
|
|
Policy.OnlyBottomUp = false;
|
|
}
|
|
|
|
bool AArch64Subtarget::enableEarlyIfConversion() const {
|
|
return EnableEarlyIfConvert;
|
|
}
|
|
|
|
std::unique_ptr<PBQPRAConstraint>
|
|
AArch64Subtarget::getCustomPBQPConstraints() const {
|
|
if (!isCortexA57())
|
|
return nullptr;
|
|
|
|
return llvm::make_unique<A57ChainingConstraint>();
|
|
}
|