llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-25 03:30:37 +00:00

History

Tim Northover d5561bb1f0 ARM: tell LLVM about zext properties of ldrexb/ldrexh

Implementing this via ComputeMaskedBits has two advantages:
  + It actually works. DAGISel doesn't deal with the chains properly
    in the previous pattern-based solution, so they never trigger.
  + The information can be used in other DAG combines, as well as the
    trivial "get rid of truncs". For example if the trunc is in a
    different basic block.

rdar://problem/16227836

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205540 91177308-0d34-0410-b5e6-96231b3b80d8

2014-04-03 15:10:35 +00:00

Analysis

Account for scalarization costs in BasicTTI::getMemoryOpCost for extending vector loads

2014-04-03 00:53:59 +00:00

Assembler

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Bindings

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Bitcode

All new elements except the last one initialized to NULL. Ideally, once parsing is complete, all elements should be non-NULL.

2014-03-27 12:08:23 +00:00

BugPoint