mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-28 06:29:45 +00:00
1a21909e98
This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236520 91177308-0d34-0410-b5e6-96231b3b80d8
286 lines
11 KiB
TableGen
286 lines
11 KiB
TableGen
//==- SystemZRegisterInfo.td - SystemZ register definitions -*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Class definitions.
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//===----------------------------------------------------------------------===//
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class SystemZReg<string n> : Register<n> {
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let Namespace = "SystemZ";
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}
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class SystemZRegWithSubregs<string n, list<Register> subregs>
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: RegisterWithSubRegs<n, subregs> {
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let Namespace = "SystemZ";
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}
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let Namespace = "SystemZ" in {
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def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32.
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def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32.
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def subreg_l64 : SubRegIndex<64, 0>;
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def subreg_h64 : SubRegIndex<64, 64>;
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def subreg_r32 : SubRegIndex<32, 32>; // Reinterpret a wider reg as 32 bits.
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def subreg_r64 : SubRegIndex<64, 64>; // Reinterpret a wider reg as 64 bits.
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def subreg_hh32 : ComposedSubRegIndex<subreg_h64, subreg_h32>;
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def subreg_hl32 : ComposedSubRegIndex<subreg_h64, subreg_l32>;
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def subreg_hr32 : ComposedSubRegIndex<subreg_h64, subreg_r32>;
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}
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// Define a register class that contains values of types TYPES and an
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// associated operand called NAME. SIZE is the size and alignment
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// of the registers and REGLIST is the list of individual registers.
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multiclass SystemZRegClass<string name, list<ValueType> types, int size,
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dag regList> {
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def AsmOperand : AsmOperandClass {
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let Name = name;
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let ParserMethod = "parse"##name;
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let RenderMethod = "addRegOperands";
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}
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def Bit : RegisterClass<"SystemZ", types, size, regList> {
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let Size = size;
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}
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def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> {
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let ParserMatchClass = !cast<AsmOperandClass>(name##"AsmOperand");
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}
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}
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//===----------------------------------------------------------------------===//
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// General-purpose registers
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//===----------------------------------------------------------------------===//
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// Lower 32 bits of one of the 16 64-bit general-purpose registers
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class GPR32<bits<16> num, string n> : SystemZReg<n> {
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let HWEncoding = num;
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}
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// One of the 16 64-bit general-purpose registers.
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class GPR64<bits<16> num, string n, GPR32 low, GPR32 high>
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: SystemZRegWithSubregs<n, [low, high]> {
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let HWEncoding = num;
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let SubRegIndices = [subreg_l32, subreg_h32];
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}
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// 8 even-odd pairs of GPR64s.
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class GPR128<bits<16> num, string n, GPR64 low, GPR64 high>
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: SystemZRegWithSubregs<n, [low, high]> {
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let HWEncoding = num;
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let SubRegIndices = [subreg_l64, subreg_h64];
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}
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// General-purpose registers
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foreach I = 0-15 in {
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def R#I#L : GPR32<I, "r"#I>;
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def R#I#H : GPR32<I, "r"#I>;
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def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>,
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DwarfRegNum<[I]>;
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}
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foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in {
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def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#!add(I, 1)#"D"),
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!cast<GPR64>("R"#I#"D")>;
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}
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/// Allocate the callee-saved R6-R13 backwards. That way they can be saved
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/// together with R14 and R15 in one prolog instruction.
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defm GR32 : SystemZRegClass<"GR32", [i32], 32,
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(add (sequence "R%uL", 0, 5),
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(sequence "R%uL", 15, 6))>;
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defm GRH32 : SystemZRegClass<"GRH32", [i32], 32,
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(add (sequence "R%uH", 0, 5),
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(sequence "R%uH", 15, 6))>;
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defm GR64 : SystemZRegClass<"GR64", [i64], 64,
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(add (sequence "R%uD", 0, 5),
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(sequence "R%uD", 15, 6))>;
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// Combine the low and high GR32s into a single class. This can only be
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// used for virtual registers if the high-word facility is available.
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defm GRX32 : SystemZRegClass<"GRX32", [i32], 32,
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(add (sequence "R%uL", 0, 5),
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(sequence "R%uH", 0, 5),
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R15L, R15H, R14L, R14H, R13L, R13H,
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R12L, R12H, R11L, R11H, R10L, R10H,
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R9L, R9H, R8L, R8H, R7L, R7H, R6L, R6H)>;
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// The architecture doesn't really have any i128 support, so model the
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// register pairs as untyped instead.
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defm GR128 : SystemZRegClass<"GR128", [untyped], 128,
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(add R0Q, R2Q, R4Q, R12Q, R10Q, R8Q, R6Q, R14Q)>;
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// Base and index registers. Everything except R0, which in an address
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// context evaluates as 0.
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defm ADDR32 : SystemZRegClass<"ADDR32", [i32], 32, (sub GR32Bit, R0L)>;
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defm ADDR64 : SystemZRegClass<"ADDR64", [i64], 64, (sub GR64Bit, R0D)>;
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// Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
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// of a GR128.
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defm ADDR128 : SystemZRegClass<"ADDR128", [untyped], 128, (sub GR128Bit, R0Q)>;
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//===----------------------------------------------------------------------===//
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// Floating-point registers
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//===----------------------------------------------------------------------===//
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// Maps FPR register numbers to their DWARF encoding.
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class DwarfMapping<int id> { int Id = id; }
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def F0Dwarf : DwarfMapping<16>;
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def F2Dwarf : DwarfMapping<17>;
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def F4Dwarf : DwarfMapping<18>;
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def F6Dwarf : DwarfMapping<19>;
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def F1Dwarf : DwarfMapping<20>;
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def F3Dwarf : DwarfMapping<21>;
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def F5Dwarf : DwarfMapping<22>;
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def F7Dwarf : DwarfMapping<23>;
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def F8Dwarf : DwarfMapping<24>;
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def F10Dwarf : DwarfMapping<25>;
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def F12Dwarf : DwarfMapping<26>;
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def F14Dwarf : DwarfMapping<27>;
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def F9Dwarf : DwarfMapping<28>;
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def F11Dwarf : DwarfMapping<29>;
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def F13Dwarf : DwarfMapping<30>;
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def F15Dwarf : DwarfMapping<31>;
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def F16Dwarf : DwarfMapping<68>;
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def F18Dwarf : DwarfMapping<69>;
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def F20Dwarf : DwarfMapping<70>;
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def F22Dwarf : DwarfMapping<71>;
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def F17Dwarf : DwarfMapping<72>;
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def F19Dwarf : DwarfMapping<73>;
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def F21Dwarf : DwarfMapping<74>;
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def F23Dwarf : DwarfMapping<75>;
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def F24Dwarf : DwarfMapping<76>;
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def F26Dwarf : DwarfMapping<77>;
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def F28Dwarf : DwarfMapping<78>;
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def F30Dwarf : DwarfMapping<79>;
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def F25Dwarf : DwarfMapping<80>;
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def F27Dwarf : DwarfMapping<81>;
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def F29Dwarf : DwarfMapping<82>;
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def F31Dwarf : DwarfMapping<83>;
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// Upper 32 bits of one of the floating-point registers
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class FPR32<bits<16> num, string n> : SystemZReg<n> {
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let HWEncoding = num;
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}
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// One of the floating-point registers.
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class FPR64<bits<16> num, string n, FPR32 high>
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: SystemZRegWithSubregs<n, [high]> {
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let HWEncoding = num;
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let SubRegIndices = [subreg_r32];
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}
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// 8 pairs of FPR64s, with a one-register gap inbetween.
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class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
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: SystemZRegWithSubregs<n, [low, high]> {
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let HWEncoding = num;
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let SubRegIndices = [subreg_l64, subreg_h64];
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}
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// Floating-point registers. Registers 16-31 require the vector facility.
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foreach I = 0-15 in {
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def F#I#S : FPR32<I, "f"#I>;
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def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
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DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
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}
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foreach I = 16-31 in {
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def F#I#S : FPR32<I, "v"#I>;
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def F#I#D : FPR64<I, "v"#I, !cast<FPR32>("F"#I#"S")>,
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DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
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}
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foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in {
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def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
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!cast<FPR64>("F"#I#"D")>;
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}
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// There's no store-multiple instruction for FPRs, so we're not fussy
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// about the order in which call-saved registers are allocated.
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defm FP32 : SystemZRegClass<"FP32", [f32], 32, (sequence "F%uS", 0, 15)>;
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defm FP64 : SystemZRegClass<"FP64", [f64], 64, (sequence "F%uD", 0, 15)>;
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defm FP128 : SystemZRegClass<"FP128", [f128], 128,
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(add F0Q, F1Q, F4Q, F5Q, F8Q, F9Q, F12Q, F13Q)>;
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//===----------------------------------------------------------------------===//
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// Vector registers
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//===----------------------------------------------------------------------===//
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// A full 128-bit vector register, with an FPR64 as its high part.
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class VR128<bits<16> num, string n, FPR64 high>
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: SystemZRegWithSubregs<n, [high]> {
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let HWEncoding = num;
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let SubRegIndices = [subreg_r64];
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}
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// Full vector registers.
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foreach I = 0-31 in {
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def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>,
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DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
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}
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// Class used to store 32-bit values in the first element of a vector
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// register. f32 scalars are used for the WLEDB and WLDEB instructions.
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defm VR32 : SystemZRegClass<"VR32", [f32, v4i8, v2i16], 32,
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(add (sequence "F%uS", 0, 7),
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(sequence "F%uS", 16, 31),
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(sequence "F%uS", 8, 15))>;
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// Class used to store 64-bit values in the upper half of a vector register.
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// The vector facility also includes scalar f64 instructions that operate
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// on the full vector register set.
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defm VR64 : SystemZRegClass<"VR64", [f64, v8i8, v4i16, v2i32, v2f32], 64,
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(add (sequence "F%uD", 0, 7),
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(sequence "F%uD", 16, 31),
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(sequence "F%uD", 8, 15))>;
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// The subset of vector registers that can be used for floating-point
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// operations too.
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defm VF128 : SystemZRegClass<"VF128",
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[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
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(sequence "V%u", 0, 15)>;
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// All vector registers.
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defm VR128 : SystemZRegClass<"VR128",
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[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
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(add (sequence "V%u", 0, 7),
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(sequence "V%u", 16, 31),
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(sequence "V%u", 8, 15))>;
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// Attaches a ValueType to a register operand, to make the instruction
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// definitions easier.
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class TypedReg<ValueType vtin, RegisterOperand opin> {
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ValueType vt = vtin;
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RegisterOperand op = opin;
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}
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def v32eb : TypedReg<f32, VR32>;
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def v64g : TypedReg<i64, VR64>;
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def v64db : TypedReg<f64, VR64>;
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def v128b : TypedReg<v16i8, VR128>;
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def v128h : TypedReg<v8i16, VR128>;
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def v128f : TypedReg<v4i32, VR128>;
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def v128g : TypedReg<v2i64, VR128>;
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def v128q : TypedReg<v16i8, VR128>;
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def v128eb : TypedReg<v4f32, VR128>;
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def v128db : TypedReg<v2f64, VR128>;
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def v128any : TypedReg<untyped, VR128>;
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//===----------------------------------------------------------------------===//
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// Other registers
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//===----------------------------------------------------------------------===//
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// The 2-bit condition code field of the PSW. Every register named in an
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// inline asm needs a class associated with it.
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def CC : SystemZReg<"cc">;
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def CCRegs : RegisterClass<"SystemZ", [i32], 32, (add CC)>;
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