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llvm-6502/lib/Target/XCore
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Richard Osborne 9e333ca445 [XCore] Whitespace fixes, no functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185519 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 07:49:03 +00:00
..
Disassembler
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InstPrinter
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MCTargetDesc
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TargetInfo
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CMakeLists.txt
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LLVMBuild.txt
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Makefile
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README.txt
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XCore.h
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XCore.td
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XCoreAsmPrinter.cpp
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
2013-06-16 20:34:27 +00:00
XCoreCallingConv.td
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XCoreFrameLowering.cpp
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XCoreFrameLowering.h
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XCoreInstrFormats.td
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XCoreInstrInfo.cpp
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
2013-06-16 20:34:27 +00:00
XCoreInstrInfo.h
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
2013-06-16 20:34:27 +00:00
XCoreInstrInfo.td
[XCore] Whitespace fixes, no functionality change.
2013-07-03 07:49:03 +00:00
XCoreISelDAGToDAG.cpp
[XCore] Fix instruction selection for zext, mkmsk instructions.
2013-07-02 14:46:34 +00:00
XCoreISelLowering.cpp
The getRegForInlineAsmConstraint function should only accept MVT value types.
2013-06-22 18:37:38 +00:00
XCoreISelLowering.h
The getRegForInlineAsmConstraint function should only accept MVT value types.
2013-06-22 18:37:38 +00:00
XCoreLowerThreadLocal.cpp
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XCoreMachineFunctionInfo.cpp
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XCoreMachineFunctionInfo.h
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XCoreMCInstLower.cpp
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XCoreMCInstLower.h
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XCoreRegisterInfo.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 21:04:35 +00:00
XCoreRegisterInfo.h
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 21:04:35 +00:00
XCoreRegisterInfo.td
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XCoreSelectionDAGInfo.cpp
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XCoreSelectionDAGInfo.h
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XCoreSubtarget.cpp
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XCoreSubtarget.h
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XCoreTargetMachine.cpp
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XCoreTargetMachine.h
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XCoreTargetObjectFile.cpp
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XCoreTargetObjectFile.h
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README.txt 

To-do
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* Instruction encodings
* Tailcalls
* Investigate loop alignment
* Add builtins