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https://github.com/c64scene-ar/llvm-6502.git
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acf7350385
We were using two instructions for similar purpose : break and predicated break. Only predicated_break was emitted and it was lowered at R600ControlFlowFinalizer to JUMP;CF_BREAK;POP. This commit simplify the situation by making AMDILCFGStructurizer emit IF_PREDICATE;BREAK;ENDIF; instead of predicated_break (which is now removed). There is no functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187510 91177308-0d34-0410-b5e6-96231b3b80d8
317 lines
10 KiB
C++
317 lines
10 KiB
C++
//===-- R600ExpandSpecialInstrs.cpp - Expand special instructions ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Vector, Reduction, and Cube instructions need to fill the entire instruction
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/// group to work correctly. This pass expands these individual instructions
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/// into several instructions that will completely fill the instruction group.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "R600RegisterInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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namespace {
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class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
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private:
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static char ID;
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const R600InstrInfo *TII;
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bool ExpandInputPerspective(MachineInstr& MI);
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bool ExpandInputConstant(MachineInstr& MI);
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public:
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R600ExpandSpecialInstrsPass(TargetMachine &tm) : MachineFunctionPass(ID),
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TII(0) { }
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virtual bool runOnMachineFunction(MachineFunction &MF);
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const char *getPassName() const {
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return "R600 Expand special instructions pass";
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}
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};
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} // End anonymous namespace
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char R600ExpandSpecialInstrsPass::ID = 0;
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FunctionPass *llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) {
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return new R600ExpandSpecialInstrsPass(TM);
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}
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bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
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TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
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const R600RegisterInfo &TRI = TII->getRegisterInfo();
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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MachineBasicBlock::iterator I = MBB.begin();
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while (I != MBB.end()) {
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MachineInstr &MI = *I;
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I = llvm::next(I);
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switch (MI.getOpcode()) {
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default: break;
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// Expand PRED_X to one of the PRED_SET instructions.
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case AMDGPU::PRED_X: {
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uint64_t Flags = MI.getOperand(3).getImm();
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// The native opcode used by PRED_X is stored as an immediate in the
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// third operand.
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MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
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MI.getOperand(2).getImm(), // opcode
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MI.getOperand(0).getReg(), // dst
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MI.getOperand(1).getReg(), // src0
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AMDGPU::ZERO); // src1
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TII->addFlag(PredSet, 0, MO_FLAG_MASK);
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if (Flags & MO_FLAG_PUSH) {
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TII->setImmOperand(PredSet, AMDGPU::OpName::update_exec_mask, 1);
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} else {
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TII->setImmOperand(PredSet, AMDGPU::OpName::update_pred, 1);
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}
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MI.eraseFromParent();
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continue;
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}
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case AMDGPU::INTERP_PAIR_XY: {
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MachineInstr *BMI;
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unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
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MI.getOperand(2).getImm());
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for (unsigned Chan = 0; Chan < 4; ++Chan) {
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unsigned DstReg;
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if (Chan < 2)
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DstReg = MI.getOperand(Chan).getReg();
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else
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DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
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BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_XY,
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DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
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if (Chan > 0) {
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BMI->bundleWithPred();
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}
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if (Chan >= 2)
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TII->addFlag(BMI, 0, MO_FLAG_MASK);
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if (Chan != 3)
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TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
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}
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MI.eraseFromParent();
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continue;
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}
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case AMDGPU::INTERP_PAIR_ZW: {
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MachineInstr *BMI;
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unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
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MI.getOperand(2).getImm());
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for (unsigned Chan = 0; Chan < 4; ++Chan) {
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unsigned DstReg;
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if (Chan < 2)
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DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y;
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else
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DstReg = MI.getOperand(Chan-2).getReg();
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BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_ZW,
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DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
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if (Chan > 0) {
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BMI->bundleWithPred();
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}
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if (Chan < 2)
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TII->addFlag(BMI, 0, MO_FLAG_MASK);
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if (Chan != 3)
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TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
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}
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MI.eraseFromParent();
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continue;
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}
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case AMDGPU::INTERP_VEC_LOAD: {
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const R600RegisterInfo &TRI = TII->getRegisterInfo();
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MachineInstr *BMI;
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unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
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MI.getOperand(1).getImm());
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unsigned DstReg = MI.getOperand(0).getReg();
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for (unsigned Chan = 0; Chan < 4; ++Chan) {
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BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_LOAD_P0,
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TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
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if (Chan > 0) {
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BMI->bundleWithPred();
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}
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if (Chan != 3)
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TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
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}
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MI.eraseFromParent();
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continue;
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}
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case AMDGPU::DOT_4: {
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const R600RegisterInfo &TRI = TII->getRegisterInfo();
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unsigned DstReg = MI.getOperand(0).getReg();
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unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
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for (unsigned Chan = 0; Chan < 4; ++Chan) {
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bool Mask = (Chan != TRI.getHWRegChan(DstReg));
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unsigned SubDstReg =
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AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
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MachineInstr *BMI =
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TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg);
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if (Chan > 0) {
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BMI->bundleWithPred();
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}
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if (Mask) {
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TII->addFlag(BMI, 0, MO_FLAG_MASK);
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}
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if (Chan != 3)
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TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
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unsigned Opcode = BMI->getOpcode();
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// While not strictly necessary from hw point of view, we force
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// all src operands of a dot4 inst to belong to the same slot.
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unsigned Src0 = BMI->getOperand(
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TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
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.getReg();
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unsigned Src1 = BMI->getOperand(
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TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
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.getReg();
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(void) Src0;
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(void) Src1;
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if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
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(TRI.getEncodingValue(Src1) & 0xff) < 127)
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assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
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}
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MI.eraseFromParent();
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continue;
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}
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}
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bool IsReduction = TII->isReductionOp(MI.getOpcode());
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bool IsVector = TII->isVector(MI);
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bool IsCube = TII->isCubeOp(MI.getOpcode());
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if (!IsReduction && !IsVector && !IsCube) {
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continue;
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}
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// Expand the instruction
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//
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// Reduction instructions:
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// T0_X = DP4 T1_XYZW, T2_XYZW
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// becomes:
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// TO_X = DP4 T1_X, T2_X
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// TO_Y (write masked) = DP4 T1_Y, T2_Y
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// TO_Z (write masked) = DP4 T1_Z, T2_Z
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// TO_W (write masked) = DP4 T1_W, T2_W
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//
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// Vector instructions:
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// T0_X = MULLO_INT T1_X, T2_X
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// becomes:
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// T0_X = MULLO_INT T1_X, T2_X
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// T0_Y (write masked) = MULLO_INT T1_X, T2_X
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// T0_Z (write masked) = MULLO_INT T1_X, T2_X
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// T0_W (write masked) = MULLO_INT T1_X, T2_X
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//
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// Cube instructions:
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// T0_XYZW = CUBE T1_XYZW
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// becomes:
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// TO_X = CUBE T1_Z, T1_Y
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// T0_Y = CUBE T1_Z, T1_X
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// T0_Z = CUBE T1_X, T1_Z
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// T0_W = CUBE T1_Y, T1_Z
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for (unsigned Chan = 0; Chan < 4; Chan++) {
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unsigned DstReg = MI.getOperand(
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TII->getOperandIdx(MI, AMDGPU::OpName::dst)).getReg();
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unsigned Src0 = MI.getOperand(
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TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg();
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unsigned Src1 = 0;
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// Determine the correct source registers
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if (!IsCube) {
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int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1);
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if (Src1Idx != -1) {
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Src1 = MI.getOperand(Src1Idx).getReg();
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}
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}
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if (IsReduction) {
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unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
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Src0 = TRI.getSubReg(Src0, SubRegIndex);
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Src1 = TRI.getSubReg(Src1, SubRegIndex);
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} else if (IsCube) {
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static const int CubeSrcSwz[] = {2, 2, 0, 1};
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unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
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unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
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Src1 = TRI.getSubReg(Src0, SubRegIndex1);
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Src0 = TRI.getSubReg(Src0, SubRegIndex0);
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}
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// Determine the correct destination registers;
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bool Mask = false;
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bool NotLast = true;
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if (IsCube) {
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unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
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DstReg = TRI.getSubReg(DstReg, SubRegIndex);
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} else {
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// Mask the write if the original instruction does not write to
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// the current Channel.
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Mask = (Chan != TRI.getHWRegChan(DstReg));
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unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
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DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
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}
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// Set the IsLast bit
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NotLast = (Chan != 3 );
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// Add the new instruction
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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case AMDGPU::CUBE_r600_pseudo:
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Opcode = AMDGPU::CUBE_r600_real;
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break;
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case AMDGPU::CUBE_eg_pseudo:
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Opcode = AMDGPU::CUBE_eg_real;
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break;
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default:
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break;
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}
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MachineInstr *NewMI =
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TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
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if (Chan != 0)
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NewMI->bundleWithPred();
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if (Mask) {
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TII->addFlag(NewMI, 0, MO_FLAG_MASK);
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}
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if (NotLast) {
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TII->addFlag(NewMI, 0, MO_FLAG_NOT_LAST);
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}
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}
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MI.eraseFromParent();
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}
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}
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return false;
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}
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