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https://github.com/c64scene-ar/llvm-6502.git
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f567a6d39b
FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182877 91177308-0d34-0410-b5e6-96231b3b80d8
59 lines
1.3 KiB
LLVM
59 lines
1.3 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s
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; Sign-extend of i1 currently not supported by fast-isel
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;define signext i1 @ret0(i1 signext %a) nounwind uwtable ssp {
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;entry:
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; ret i1 %a
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;}
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define zeroext i1 @ret1(i1 signext %a) nounwind uwtable ssp {
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entry:
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; CHECK: ret1
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; CHECK: and r0, r0, #1
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; CHECK: bx lr
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ret i1 %a
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}
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define signext i8 @ret2(i8 signext %a) nounwind uwtable ssp {
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entry:
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; CHECK: ret2
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; CHECK: sxtb r0, r0
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; CHECK: bx lr
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ret i8 %a
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}
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define zeroext i8 @ret3(i8 signext %a) nounwind uwtable ssp {
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entry:
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; CHECK: ret3
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; CHECK: uxtb r0, r0
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; CHECK: bx lr
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ret i8 %a
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}
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define signext i16 @ret4(i16 signext %a) nounwind uwtable ssp {
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entry:
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; CHECK: ret4
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; CHECK: sxth r0, r0
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; CHECK: bx lr
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ret i16 %a
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}
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define zeroext i16 @ret5(i16 signext %a) nounwind uwtable ssp {
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entry:
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; CHECK: ret5
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; CHECK: uxth r0, r0
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; CHECK: bx lr
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ret i16 %a
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}
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define i16 @ret6(i16 %a) nounwind uwtable ssp {
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entry:
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; CHECK: ret6
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; CHECK-NOT: uxth
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; CHECK-NOT: sxth
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; CHECK: bx lr
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ret i16 %a
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}
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