mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 07:29:55 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129913 91177308-0d34-0410-b5e6-96231b3b80d8
492 lines
15 KiB
TableGen
492 lines
15 KiB
TableGen
//===- PTXRegisterInfo.td - PTX Register defs ----------------*- tblgen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the PTX register file
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//===----------------------------------------------------------------------===//
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class PTXReg<string n> : Register<n> {
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let Namespace = "PTX";
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}
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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///===- Predicate Registers -----------------------------------------------===//
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def P0 : PTXReg<"p0">;
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def P1 : PTXReg<"p1">;
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def P2 : PTXReg<"p2">;
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def P3 : PTXReg<"p3">;
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def P4 : PTXReg<"p4">;
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def P5 : PTXReg<"p5">;
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def P6 : PTXReg<"p6">;
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def P7 : PTXReg<"p7">;
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def P8 : PTXReg<"p8">;
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def P9 : PTXReg<"p9">;
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def P10 : PTXReg<"p10">;
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def P11 : PTXReg<"p11">;
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def P12 : PTXReg<"p12">;
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def P13 : PTXReg<"p13">;
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def P14 : PTXReg<"p14">;
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def P15 : PTXReg<"p15">;
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def P16 : PTXReg<"p16">;
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def P17 : PTXReg<"p17">;
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def P18 : PTXReg<"p18">;
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def P19 : PTXReg<"p19">;
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def P20 : PTXReg<"p20">;
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def P21 : PTXReg<"p21">;
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def P22 : PTXReg<"p22">;
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def P23 : PTXReg<"p23">;
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def P24 : PTXReg<"p24">;
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def P25 : PTXReg<"p25">;
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def P26 : PTXReg<"p26">;
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def P27 : PTXReg<"p27">;
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def P28 : PTXReg<"p28">;
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def P29 : PTXReg<"p29">;
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def P30 : PTXReg<"p30">;
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def P31 : PTXReg<"p31">;
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def P32 : PTXReg<"p32">;
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def P33 : PTXReg<"p33">;
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def P34 : PTXReg<"p34">;
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def P35 : PTXReg<"p35">;
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def P36 : PTXReg<"p36">;
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def P37 : PTXReg<"p37">;
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def P38 : PTXReg<"p38">;
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def P39 : PTXReg<"p39">;
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def P40 : PTXReg<"p40">;
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def P41 : PTXReg<"p41">;
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def P42 : PTXReg<"p42">;
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def P43 : PTXReg<"p43">;
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def P44 : PTXReg<"p44">;
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def P45 : PTXReg<"p45">;
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def P46 : PTXReg<"p46">;
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def P47 : PTXReg<"p47">;
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def P48 : PTXReg<"p48">;
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def P49 : PTXReg<"p49">;
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def P50 : PTXReg<"p50">;
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def P51 : PTXReg<"p51">;
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def P52 : PTXReg<"p52">;
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def P53 : PTXReg<"p53">;
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def P54 : PTXReg<"p54">;
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def P55 : PTXReg<"p55">;
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def P56 : PTXReg<"p56">;
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def P57 : PTXReg<"p57">;
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def P58 : PTXReg<"p58">;
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def P59 : PTXReg<"p59">;
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def P60 : PTXReg<"p60">;
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def P61 : PTXReg<"p61">;
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def P62 : PTXReg<"p62">;
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def P63 : PTXReg<"p63">;
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///===- 16-bit Integer Registers ------------------------------------------===//
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def RH0 : PTXReg<"rh0">;
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def RH1 : PTXReg<"rh1">;
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def RH2 : PTXReg<"rh2">;
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def RH3 : PTXReg<"rh3">;
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def RH4 : PTXReg<"rh4">;
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def RH5 : PTXReg<"rh5">;
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def RH6 : PTXReg<"rh6">;
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def RH7 : PTXReg<"rh7">;
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def RH8 : PTXReg<"rh8">;
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def RH9 : PTXReg<"rh9">;
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def RH10 : PTXReg<"rh10">;
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def RH11 : PTXReg<"rh11">;
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def RH12 : PTXReg<"rh12">;
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def RH13 : PTXReg<"rh13">;
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def RH14 : PTXReg<"rh14">;
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def RH15 : PTXReg<"rh15">;
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def RH16 : PTXReg<"rh16">;
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def RH17 : PTXReg<"rh17">;
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def RH18 : PTXReg<"rh18">;
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def RH19 : PTXReg<"rh19">;
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def RH20 : PTXReg<"rh20">;
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def RH21 : PTXReg<"rh21">;
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def RH22 : PTXReg<"rh22">;
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def RH23 : PTXReg<"rh23">;
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def RH24 : PTXReg<"rh24">;
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def RH25 : PTXReg<"rh25">;
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def RH26 : PTXReg<"rh26">;
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def RH27 : PTXReg<"rh27">;
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def RH28 : PTXReg<"rh28">;
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def RH29 : PTXReg<"rh29">;
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def RH30 : PTXReg<"rh30">;
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def RH31 : PTXReg<"rh31">;
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def RH32 : PTXReg<"rh32">;
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def RH33 : PTXReg<"rh33">;
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def RH34 : PTXReg<"rh34">;
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def RH35 : PTXReg<"rh35">;
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def RH36 : PTXReg<"rh36">;
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def RH37 : PTXReg<"rh37">;
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def RH38 : PTXReg<"rh38">;
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def RH39 : PTXReg<"rh39">;
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def RH40 : PTXReg<"rh40">;
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def RH41 : PTXReg<"rh41">;
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def RH42 : PTXReg<"rh42">;
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def RH43 : PTXReg<"rh43">;
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def RH44 : PTXReg<"rh44">;
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def RH45 : PTXReg<"rh45">;
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def RH46 : PTXReg<"rh46">;
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def RH47 : PTXReg<"rh47">;
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def RH48 : PTXReg<"rh48">;
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def RH49 : PTXReg<"rh49">;
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def RH50 : PTXReg<"rh50">;
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def RH51 : PTXReg<"rh51">;
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def RH52 : PTXReg<"rh52">;
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def RH53 : PTXReg<"rh53">;
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def RH54 : PTXReg<"rh54">;
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def RH55 : PTXReg<"rh55">;
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def RH56 : PTXReg<"rh56">;
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def RH57 : PTXReg<"rh57">;
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def RH58 : PTXReg<"rh58">;
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def RH59 : PTXReg<"rh59">;
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def RH60 : PTXReg<"rh60">;
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def RH61 : PTXReg<"rh61">;
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def RH62 : PTXReg<"rh62">;
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def RH63 : PTXReg<"rh63">;
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///===- 32-bit Integer Registers ------------------------------------------===//
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def R0 : PTXReg<"r0">;
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def R1 : PTXReg<"r1">;
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def R2 : PTXReg<"r2">;
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def R3 : PTXReg<"r3">;
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def R4 : PTXReg<"r4">;
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def R5 : PTXReg<"r5">;
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def R6 : PTXReg<"r6">;
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def R7 : PTXReg<"r7">;
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def R8 : PTXReg<"r8">;
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def R9 : PTXReg<"r9">;
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def R10 : PTXReg<"r10">;
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def R11 : PTXReg<"r11">;
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def R12 : PTXReg<"r12">;
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def R13 : PTXReg<"r13">;
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def R14 : PTXReg<"r14">;
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def R15 : PTXReg<"r15">;
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def R16 : PTXReg<"r16">;
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def R17 : PTXReg<"r17">;
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def R18 : PTXReg<"r18">;
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def R19 : PTXReg<"r19">;
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def R20 : PTXReg<"r20">;
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def R21 : PTXReg<"r21">;
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def R22 : PTXReg<"r22">;
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def R23 : PTXReg<"r23">;
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def R24 : PTXReg<"r24">;
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def R25 : PTXReg<"r25">;
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def R26 : PTXReg<"r26">;
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def R27 : PTXReg<"r27">;
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def R28 : PTXReg<"r28">;
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def R29 : PTXReg<"r29">;
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def R30 : PTXReg<"r30">;
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def R31 : PTXReg<"r31">;
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def R32 : PTXReg<"r32">;
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def R33 : PTXReg<"r33">;
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def R34 : PTXReg<"r34">;
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def R35 : PTXReg<"r35">;
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def R36 : PTXReg<"r36">;
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def R37 : PTXReg<"r37">;
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def R38 : PTXReg<"r38">;
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def R39 : PTXReg<"r39">;
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def R40 : PTXReg<"r40">;
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def R41 : PTXReg<"r41">;
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def R42 : PTXReg<"r42">;
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def R43 : PTXReg<"r43">;
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def R44 : PTXReg<"r44">;
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def R45 : PTXReg<"r45">;
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def R46 : PTXReg<"r46">;
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def R47 : PTXReg<"r47">;
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def R48 : PTXReg<"r48">;
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def R49 : PTXReg<"r49">;
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def R50 : PTXReg<"r50">;
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def R51 : PTXReg<"r51">;
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def R52 : PTXReg<"r52">;
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def R53 : PTXReg<"r53">;
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def R54 : PTXReg<"r54">;
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def R55 : PTXReg<"r55">;
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def R56 : PTXReg<"r56">;
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def R57 : PTXReg<"r57">;
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def R58 : PTXReg<"r58">;
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def R59 : PTXReg<"r59">;
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def R60 : PTXReg<"r60">;
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def R61 : PTXReg<"r61">;
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def R62 : PTXReg<"r62">;
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def R63 : PTXReg<"r63">;
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///===- 64-bit Integer Registers ------------------------------------------===//
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def RD0 : PTXReg<"rd0">;
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def RD1 : PTXReg<"rd1">;
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def RD2 : PTXReg<"rd2">;
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def RD3 : PTXReg<"rd3">;
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def RD4 : PTXReg<"rd4">;
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def RD5 : PTXReg<"rd5">;
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def RD6 : PTXReg<"rd6">;
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def RD7 : PTXReg<"rd7">;
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def RD8 : PTXReg<"rd8">;
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def RD9 : PTXReg<"rd9">;
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def RD10 : PTXReg<"rd10">;
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def RD11 : PTXReg<"rd11">;
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def RD12 : PTXReg<"rd12">;
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def RD13 : PTXReg<"rd13">;
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def RD14 : PTXReg<"rd14">;
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def RD15 : PTXReg<"rd15">;
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def RD16 : PTXReg<"rd16">;
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def RD17 : PTXReg<"rd17">;
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def RD18 : PTXReg<"rd18">;
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def RD19 : PTXReg<"rd19">;
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def RD20 : PTXReg<"rd20">;
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def RD21 : PTXReg<"rd21">;
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def RD22 : PTXReg<"rd22">;
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def RD23 : PTXReg<"rd23">;
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def RD24 : PTXReg<"rd24">;
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def RD25 : PTXReg<"rd25">;
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def RD26 : PTXReg<"rd26">;
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def RD27 : PTXReg<"rd27">;
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def RD28 : PTXReg<"rd28">;
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def RD29 : PTXReg<"rd29">;
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def RD30 : PTXReg<"rd30">;
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def RD31 : PTXReg<"rd31">;
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def RD32 : PTXReg<"rd32">;
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def RD33 : PTXReg<"rd33">;
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def RD34 : PTXReg<"rd34">;
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def RD35 : PTXReg<"rd35">;
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def RD36 : PTXReg<"rd36">;
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def RD37 : PTXReg<"rd37">;
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def RD38 : PTXReg<"rd38">;
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def RD39 : PTXReg<"rd39">;
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def RD40 : PTXReg<"rd40">;
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def RD41 : PTXReg<"rd41">;
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def RD42 : PTXReg<"rd42">;
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def RD43 : PTXReg<"rd43">;
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def RD44 : PTXReg<"rd44">;
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def RD45 : PTXReg<"rd45">;
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def RD46 : PTXReg<"rd46">;
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def RD47 : PTXReg<"rd47">;
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def RD48 : PTXReg<"rd48">;
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def RD49 : PTXReg<"rd49">;
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def RD50 : PTXReg<"rd50">;
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def RD51 : PTXReg<"rd51">;
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def RD52 : PTXReg<"rd52">;
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def RD53 : PTXReg<"rd53">;
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def RD54 : PTXReg<"rd54">;
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def RD55 : PTXReg<"rd55">;
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def RD56 : PTXReg<"rd56">;
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def RD57 : PTXReg<"rd57">;
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def RD58 : PTXReg<"rd58">;
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def RD59 : PTXReg<"rd59">;
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def RD60 : PTXReg<"rd60">;
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def RD61 : PTXReg<"rd61">;
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def RD62 : PTXReg<"rd62">;
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def RD63 : PTXReg<"rd63">;
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///===- 32-bit Floating-Point Registers -----------------------------------===//
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def F0 : PTXReg<"f0">;
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def F1 : PTXReg<"f1">;
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def F2 : PTXReg<"f2">;
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def F3 : PTXReg<"f3">;
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def F4 : PTXReg<"f4">;
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def F5 : PTXReg<"f5">;
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def F6 : PTXReg<"f6">;
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def F7 : PTXReg<"f7">;
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def F8 : PTXReg<"f8">;
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def F9 : PTXReg<"f9">;
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def F10 : PTXReg<"f10">;
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def F11 : PTXReg<"f11">;
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def F12 : PTXReg<"f12">;
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def F13 : PTXReg<"f13">;
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def F14 : PTXReg<"f14">;
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def F15 : PTXReg<"f15">;
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def F16 : PTXReg<"f16">;
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def F17 : PTXReg<"f17">;
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def F18 : PTXReg<"f18">;
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def F19 : PTXReg<"f19">;
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def F20 : PTXReg<"f20">;
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def F21 : PTXReg<"f21">;
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def F22 : PTXReg<"f22">;
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def F23 : PTXReg<"f23">;
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def F24 : PTXReg<"f24">;
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def F25 : PTXReg<"f25">;
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def F26 : PTXReg<"f26">;
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def F27 : PTXReg<"f27">;
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def F28 : PTXReg<"f28">;
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def F29 : PTXReg<"f29">;
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def F30 : PTXReg<"f30">;
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def F31 : PTXReg<"f31">;
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def F32 : PTXReg<"f32">;
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def F33 : PTXReg<"f33">;
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def F34 : PTXReg<"f34">;
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def F35 : PTXReg<"f35">;
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def F36 : PTXReg<"f36">;
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def F37 : PTXReg<"f37">;
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def F38 : PTXReg<"f38">;
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def F39 : PTXReg<"f39">;
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def F40 : PTXReg<"f40">;
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def F41 : PTXReg<"f41">;
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def F42 : PTXReg<"f42">;
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def F43 : PTXReg<"f43">;
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def F44 : PTXReg<"f44">;
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def F45 : PTXReg<"f45">;
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def F46 : PTXReg<"f46">;
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def F47 : PTXReg<"f47">;
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def F48 : PTXReg<"f48">;
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def F49 : PTXReg<"f49">;
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def F50 : PTXReg<"f50">;
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def F51 : PTXReg<"f51">;
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def F52 : PTXReg<"f52">;
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def F53 : PTXReg<"f53">;
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def F54 : PTXReg<"f54">;
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def F55 : PTXReg<"f55">;
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def F56 : PTXReg<"f56">;
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def F57 : PTXReg<"f57">;
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def F58 : PTXReg<"f58">;
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def F59 : PTXReg<"f59">;
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def F60 : PTXReg<"f60">;
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def F61 : PTXReg<"f61">;
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def F62 : PTXReg<"f62">;
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def F63 : PTXReg<"f63">;
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///===- 64-bit Floating-Point Registers -----------------------------------===//
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def FD0 : PTXReg<"fd0">;
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def FD1 : PTXReg<"fd1">;
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def FD2 : PTXReg<"fd2">;
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def FD3 : PTXReg<"fd3">;
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def FD4 : PTXReg<"fd4">;
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def FD5 : PTXReg<"fd5">;
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def FD6 : PTXReg<"fd6">;
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def FD7 : PTXReg<"fd7">;
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def FD8 : PTXReg<"fd8">;
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def FD9 : PTXReg<"fd9">;
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def FD10 : PTXReg<"fd10">;
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def FD11 : PTXReg<"fd11">;
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def FD12 : PTXReg<"fd12">;
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def FD13 : PTXReg<"fd13">;
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def FD14 : PTXReg<"fd14">;
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def FD15 : PTXReg<"fd15">;
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def FD16 : PTXReg<"fd16">;
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def FD17 : PTXReg<"fd17">;
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def FD18 : PTXReg<"fd18">;
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def FD19 : PTXReg<"fd19">;
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def FD20 : PTXReg<"fd20">;
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def FD21 : PTXReg<"fd21">;
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def FD22 : PTXReg<"fd22">;
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def FD23 : PTXReg<"fd23">;
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def FD24 : PTXReg<"fd24">;
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def FD25 : PTXReg<"fd25">;
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def FD26 : PTXReg<"fd26">;
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def FD27 : PTXReg<"fd27">;
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def FD28 : PTXReg<"fd28">;
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def FD29 : PTXReg<"fd29">;
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def FD30 : PTXReg<"fd30">;
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def FD31 : PTXReg<"fd31">;
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def FD32 : PTXReg<"fd32">;
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def FD33 : PTXReg<"fd33">;
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def FD34 : PTXReg<"fd34">;
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def FD35 : PTXReg<"fd35">;
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def FD36 : PTXReg<"fd36">;
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def FD37 : PTXReg<"fd37">;
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def FD38 : PTXReg<"fd38">;
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def FD39 : PTXReg<"fd39">;
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def FD40 : PTXReg<"fd40">;
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def FD41 : PTXReg<"fd41">;
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def FD42 : PTXReg<"fd42">;
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def FD43 : PTXReg<"fd43">;
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def FD44 : PTXReg<"fd44">;
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def FD45 : PTXReg<"fd45">;
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def FD46 : PTXReg<"f4d6">;
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def FD47 : PTXReg<"fd47">;
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def FD48 : PTXReg<"fd48">;
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def FD49 : PTXReg<"fd49">;
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def FD50 : PTXReg<"fd50">;
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def FD51 : PTXReg<"fd51">;
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def FD52 : PTXReg<"fd52">;
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def FD53 : PTXReg<"fd53">;
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def FD54 : PTXReg<"fd54">;
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def FD55 : PTXReg<"fd55">;
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def FD56 : PTXReg<"fd56">;
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def FD57 : PTXReg<"fd57">;
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def FD58 : PTXReg<"fd58">;
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def FD59 : PTXReg<"fd59">;
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def FD60 : PTXReg<"fd60">;
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def FD61 : PTXReg<"fd61">;
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def FD62 : PTXReg<"fd62">;
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def FD63 : PTXReg<"fd63">;
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//===----------------------------------------------------------------------===//
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// Register classes
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//===----------------------------------------------------------------------===//
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def Preds : RegisterClass<"PTX", [i1], 8,
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[P0, P1, P2, P3, P4, P5, P6, P7,
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P8, P9, P10, P11, P12, P13, P14, P15,
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P16, P17, P18, P19, P20, P21, P22, P23,
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P24, P25, P26, P27, P28, P29, P30, P31,
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P32, P33, P34, P35, P36, P37, P38, P39,
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P40, P41, P42, P43, P44, P45, P46, P47,
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P48, P49, P50, P51, P52, P53, P54, P55,
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P56, P57, P58, P59, P60, P61, P62, P63]>;
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def RRegu16 : RegisterClass<"PTX", [i16], 16,
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[RH0, RH1, RH2, RH3, RH4, RH5, RH6, RH7,
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RH8, RH9, RH10, RH11, RH12, RH13, RH14, RH15,
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RH16, RH17, RH18, RH19, RH20, RH21, RH22, RH23,
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RH24, RH25, RH26, RH27, RH28, RH29, RH30, RH31,
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RH32, RH33, RH34, RH35, RH36, RH37, RH38, RH39,
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RH40, RH41, RH42, RH43, RH44, RH45, RH46, RH47,
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RH48, RH49, RH50, RH51, RH52, RH53, RH54, RH55,
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RH56, RH57, RH58, RH59, RH60, RH61, RH62, RH63]>;
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def RRegu32 : RegisterClass<"PTX", [i32], 32,
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[R0, R1, R2, R3, R4, R5, R6, R7,
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R8, R9, R10, R11, R12, R13, R14, R15,
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R16, R17, R18, R19, R20, R21, R22, R23,
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R24, R25, R26, R27, R28, R29, R30, R31,
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R32, R33, R34, R35, R36, R37, R38, R39,
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R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55,
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R56, R57, R58, R59, R60, R61, R62, R63]>;
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def RRegu64 : RegisterClass<"PTX", [i64], 64,
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[RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7,
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RD8, RD9, RD10, RD11, RD12, RD13, RD14, RD15,
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RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23,
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RD24, RD25, RD26, RD27, RD28, RD29, RD30, RD31,
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RD32, RD33, RD34, RD35, RD36, RD37, RD38, RD39,
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RD40, RD41, RD42, RD43, RD44, RD45, RD46, RD47,
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RD48, RD49, RD50, RD51, RD52, RD53, RD54, RD55,
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RD56, RD57, RD58, RD59, RD60, RD61, RD62, RD63]>;
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def RRegf32 : RegisterClass<"PTX", [f32], 32,
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[F0, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23,
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F24, F25, F26, F27, F28, F29, F30, F31,
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F32, F33, F34, F35, F36, F37, F38, F39,
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F40, F41, F42, F43, F44, F45, F46, F47,
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F48, F49, F50, F51, F52, F53, F54, F55,
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F56, F57, F58, F59, F60, F61, F62, F63]>;
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def RRegf64 : RegisterClass<"PTX", [f64], 64,
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[FD0, FD1, FD2, FD3, FD4, FD5, FD6, FD7,
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FD8, FD9, FD10, FD11, FD12, FD13, FD14, FD15,
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FD16, FD17, FD18, FD19, FD20, FD21, FD22, FD23,
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FD24, FD25, FD26, FD27, FD28, FD29, FD30, FD31,
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FD32, FD33, FD34, FD35, FD36, FD37, FD38, FD39,
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FD40, FD41, FD42, FD43, FD44, FD45, FD46, FD47,
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FD48, FD49, FD50, FD51, FD52, FD53, FD54, FD55,
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FD56, FD57, FD58, FD59, FD60, FD61, FD62, FD63]>;
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