mirror of
https://github.com/c64scene-ar/llvm-6502.git
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d8149c1bef
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
44 lines
870 B
LLVM
44 lines
870 B
LLVM
; RUN: llc < %s -march=ptx32 | FileCheck %s
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define ptx_device i32 @t1(i32 %x, i32 %y) {
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; CHECK: shr.u32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
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%z = lshr i32 %x, %y
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; CHECK: ret;
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ret i32 %z
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}
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define ptx_device i32 @t2(i32 %x) {
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; CHECK: shr.u32 r{{[0-9]+}}, r{{[0-9]+}}, 3
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%z = lshr i32 %x, 3
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; CHECK: ret;
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ret i32 %z
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}
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define ptx_device i32 @t3(i32 %x) {
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; CHECK: shr.u32 r{{[0-9]+}}, 3, r{{[0-9]+}}
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%z = lshr i32 3, %x
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; CHECK: ret;
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ret i32 %z
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}
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define ptx_device i32 @t4(i32 %x, i32 %y) {
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; CHECK: shr.s32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
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%z = ashr i32 %x, %y
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; CHECK: ret;
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ret i32 %z
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}
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define ptx_device i32 @t5(i32 %x) {
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; CHECK: shr.s32 r{{[0-9]+}}, r{{[0-9]+}}, 3
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%z = ashr i32 %x, 3
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; CHECK: ret;
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ret i32 %z
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}
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define ptx_device i32 @t6(i32 %x) {
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; CHECK: shr.s32 r{{[0-9]+}}, -3, r{{[0-9]+}}
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%z = ashr i32 -3, %x
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; CHECK: ret;
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ret i32 %z
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}
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