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1b4aeb5cec
used in the SparcV9 backend really have anything to do with TargetInstrInfo, so we're converting them into regular old global functions and moving their declarations to SparcV9InstrSelectionSupport.h. (They're mostly used as helper functions for SparcV9InstrSelection.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15277 91177308-0d34-0410-b5e6-96231b3b80d8
76 lines
2.6 KiB
C++
76 lines
2.6 KiB
C++
//===-- SparcV9InstrInfo.h - Define TargetInstrInfo for SparcV9 -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class contains information about individual instructions.
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// Also see the SparcV9MachineInstrDesc array, which can be found in
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// SparcV9TargetMachine.cpp.
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// Other information is computed on demand, and most such functions
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// default to member functions in base class TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARCV9INSTRINFO_H
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#define SPARCV9INSTRINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "SparcV9Internals.h"
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#include "SparcV9RegisterInfo.h"
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namespace llvm {
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struct SparcV9InstrInfo : public TargetInstrInfo {
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const SparcV9RegisterInfo RI;
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public:
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SparcV9InstrInfo();
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
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// All immediate constants are in position 1 except the
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// store instructions and SETxx.
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//
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virtual int getImmedConstantPos(MachineOpCode opCode) const {
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bool ignore;
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if (this->maxImmedConstant(opCode, ignore) != 0) {
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// 1st store opcode
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assert(! this->isStore((MachineOpCode) V9::STBr - 1));
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// last store opcode
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assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
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if (opCode == V9::SETSW || opCode == V9::SETUW ||
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opCode == V9::SETX || opCode == V9::SETHI)
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return 0;
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if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
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return 2;
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return 1;
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}
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else
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return -1;
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}
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virtual bool hasResultInterlock(MachineOpCode opCode) const
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{
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// All UltraSPARC instructions have interlocks (note that delay slots
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// are not considered here).
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// However, instructions that use the result of an FCMP produce a
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// 9-cycle stall if they are issued less than 3 cycles after the FCMP.
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// Force the compiler to insert a software interlock (i.e., gap of
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// 2 other groups, including NOPs if necessary).
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return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
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}
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};
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} // End llvm namespace
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#endif
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