mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
2.2 KiB
LLVM
56 lines
2.2 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
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;REQUIRES: asserts
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define void @main() {
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main_body:
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%0 = load <4 x float>, <4 x float> addrspace(9)* null
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%1 = extractelement <4 x float> %0, i32 3
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%2 = fptosi float %1 to i32
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%3 = bitcast i32 %2 to float
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%4 = load <4 x float>, <4 x float> addrspace(9)* null
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%5 = extractelement <4 x float> %4, i32 0
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%6 = load <4 x float>, <4 x float> addrspace(9)* null
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%7 = extractelement <4 x float> %6, i32 1
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%8 = load <4 x float>, <4 x float> addrspace(9)* null
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%9 = extractelement <4 x float> %8, i32 2
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br label %LOOP
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LOOP: ; preds = %ENDIF, %main_body
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%temp4.0 = phi float [ %5, %main_body ], [ %temp5.0, %ENDIF ]
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%temp5.0 = phi float [ %7, %main_body ], [ %temp6.0, %ENDIF ]
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%temp6.0 = phi float [ %9, %main_body ], [ %temp4.0, %ENDIF ]
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%temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %27, %ENDIF ]
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%10 = bitcast float %temp8.0 to i32
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%11 = bitcast float %3 to i32
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%12 = icmp sge i32 %10, %11
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%13 = sext i1 %12 to i32
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%14 = bitcast i32 %13 to float
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%15 = bitcast float %14 to i32
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%16 = icmp ne i32 %15, 0
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br i1 %16, label %IF, label %ENDIF
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IF: ; preds = %LOOP
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%17 = call float @llvm.AMDIL.clamp.(float %temp4.0, float 0.000000e+00, float 1.000000e+00)
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%18 = call float @llvm.AMDIL.clamp.(float %temp5.0, float 0.000000e+00, float 1.000000e+00)
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%19 = call float @llvm.AMDIL.clamp.(float %temp6.0, float 0.000000e+00, float 1.000000e+00)
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%20 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
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%21 = insertelement <4 x float> undef, float %17, i32 0
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%22 = insertelement <4 x float> %21, float %18, i32 1
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%23 = insertelement <4 x float> %22, float %19, i32 2
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%24 = insertelement <4 x float> %23, float %20, i32 3
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call void @llvm.R600.store.swizzle(<4 x float> %24, i32 0, i32 0)
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ret void
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ENDIF: ; preds = %LOOP
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%25 = bitcast float %temp8.0 to i32
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%26 = add i32 %25, 1
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%27 = bitcast i32 %26 to float
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br label %LOOP
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}
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declare float @llvm.AMDIL.clamp.(float, float, float) #0
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declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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attributes #0 = { readnone }
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