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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204216 91177308-0d34-0410-b5e6-96231b3b80d8
236 lines
7.4 KiB
C++
236 lines
7.4 KiB
C++
//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "X86TargetMachine.h"
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#include "X86.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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extern "C" void LLVMInitializeX86Target() {
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// Register the target.
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RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
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RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
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}
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void X86TargetMachine::anchor() { }
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static std::string computeDataLayout(const X86Subtarget &ST) {
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// X86 is little endian
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std::string Ret = "e";
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Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
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// X86 and x32 have 32 bit pointers.
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if (ST.isTarget64BitILP32() || !ST.is64Bit())
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Ret += "-p:32:32";
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// Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
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if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows() ||
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ST.isTargetNaCl())
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Ret += "-i64:64";
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else
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Ret += "-f64:32:64";
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// Some ABIs align long double to 128 bits, others to 32.
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if (ST.isTargetNaCl())
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; // No f80
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else if (ST.is64Bit() || ST.isTargetDarwin())
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Ret += "-f80:128";
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else
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Ret += "-f80:32";
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// The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
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if (ST.is64Bit())
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Ret += "-n8:16:32:64";
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else
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Ret += "-n8:16:32";
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// The stack is aligned to 32 bits on some ABIs and 128 bits on others.
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if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetWindows()))
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Ret += "-S32";
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else
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Ret += "-S128";
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return Ret;
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}
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/// X86TargetMachine ctor - Create an X86 target.
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///
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X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, Options.StackAlignmentOverride),
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FrameLowering(*this, Subtarget),
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InstrItins(Subtarget.getInstrItineraryData()),
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DL(computeDataLayout(*getSubtargetImpl())),
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InstrInfo(*this),
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TLInfo(*this),
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TSInfo(*this),
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JITInfo(*this) {
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// Determine the PICStyle based on the target selected.
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if (getRelocationModel() == Reloc::Static) {
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// Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
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Subtarget.setPICStyle(PICStyles::None);
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} else if (Subtarget.is64Bit()) {
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// PIC in 64 bit mode is always rip-rel.
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Subtarget.setPICStyle(PICStyles::RIPRel);
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} else if (Subtarget.isTargetCOFF()) {
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Subtarget.setPICStyle(PICStyles::None);
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} else if (Subtarget.isTargetDarwin()) {
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if (getRelocationModel() == Reloc::PIC_)
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Subtarget.setPICStyle(PICStyles::StubPIC);
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else {
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assert(getRelocationModel() == Reloc::DynamicNoPIC);
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Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
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}
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} else if (Subtarget.isTargetELF()) {
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Subtarget.setPICStyle(PICStyles::GOT);
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}
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// default to hard float ABI
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if (Options.FloatABIType == FloatABI::Default)
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this->Options.FloatABIType = FloatABI::Hard;
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initAsmInfo();
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}
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//===----------------------------------------------------------------------===//
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// Command line options for x86
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//===----------------------------------------------------------------------===//
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static cl::opt<bool>
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UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
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cl::desc("Minimize AVX to SSE transition penalty"),
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cl::init(true));
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// Temporary option to control early if-conversion for x86 while adding machine
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// models.
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static cl::opt<bool>
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X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
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cl::desc("Enable early if-conversion on X86"));
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//===----------------------------------------------------------------------===//
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// X86 Analysis Pass Setup
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//===----------------------------------------------------------------------===//
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void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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// Add first the target-independent BasicTTI pass, then our X86 pass. This
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// allows the X86 pass to delegate to the target independent layer when
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// appropriate.
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PM.add(createBasicTargetTransformInfoPass(this));
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PM.add(createX86TargetTransformInfoPass(this));
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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namespace {
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/// X86 Code Generator Pass Configuration Options.
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class X86PassConfig : public TargetPassConfig {
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public:
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X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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X86TargetMachine &getX86TargetMachine() const {
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return getTM<X86TargetMachine>();
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}
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const X86Subtarget &getX86Subtarget() const {
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return *getX86TargetMachine().getSubtargetImpl();
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}
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bool addInstSelector() override;
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bool addILPOpts() override;
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bool addPreRegAlloc() override;
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bool addPostRegAlloc() override;
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bool addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
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return new X86PassConfig(this, PM);
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}
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bool X86PassConfig::addInstSelector() {
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// Install an instruction selector.
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addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
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// For ELF, cleanup any local-dynamic TLS accesses.
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if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
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addPass(createCleanupLocalDynamicTLSPass());
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// For 32-bit, prepend instructions to set the "global base reg" for PIC.
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if (!getX86Subtarget().is64Bit())
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addPass(createGlobalBaseRegPass());
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return false;
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}
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bool X86PassConfig::addILPOpts() {
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if (X86EarlyIfConv && getX86Subtarget().hasCMov()) {
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addPass(&EarlyIfConverterID);
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return true;
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}
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return false;
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}
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bool X86PassConfig::addPreRegAlloc() {
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return false; // -print-machineinstr shouldn't print after this.
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}
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bool X86PassConfig::addPostRegAlloc() {
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addPass(createX86FloatingPointStackifierPass());
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return true; // -print-machineinstr should print after this.
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}
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bool X86PassConfig::addPreEmitPass() {
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bool ShouldPrint = false;
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if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
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addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
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ShouldPrint = true;
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}
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if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
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addPass(createX86IssueVZeroUpperPass());
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ShouldPrint = true;
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}
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if (getOptLevel() != CodeGenOpt::None &&
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getX86Subtarget().padShortFunctions()) {
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addPass(createX86PadShortFunctions());
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ShouldPrint = true;
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}
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if (getOptLevel() != CodeGenOpt::None &&
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getX86Subtarget().LEAusesAG()){
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addPass(createX86FixupLEAs());
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ShouldPrint = true;
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}
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return ShouldPrint;
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}
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bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
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JITCodeEmitter &JCE) {
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PM.add(createX86JITCodeEmitterPass(*this, JCE));
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return false;
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}
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