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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53196 91177308-0d34-0410-b5e6-96231b3b80d8
414 lines
13 KiB
C++
414 lines
13 KiB
C++
//===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the machine register scavenger. It can provide
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// information, such as unused registers, at any point in a machine basic block.
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// It also provides a mechanism to make registers available by evicting them to
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// spill slots.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reg-scavenging"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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/// RedefinesSuperRegPart - Return true if the specified register is redefining
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/// part of a super-register.
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static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
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const TargetRegisterInfo *TRI) {
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bool SeenSuperUse = false;
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bool SeenSuperDef = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isRegister())
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continue;
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if (TRI->isSuperRegister(SubReg, MO.getReg())) {
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if (MO.isUse())
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SeenSuperUse = true;
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else if (MO.isImplicit())
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SeenSuperDef = true;
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}
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}
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return SeenSuperDef && SeenSuperUse;
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}
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static bool RedefinesSuperRegPart(const MachineInstr *MI,
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const MachineOperand &MO,
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const TargetRegisterInfo *TRI) {
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assert(MO.isRegister() && MO.isDef() && "Not a register def!");
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return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
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}
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/// setUsed - Set the register and its sub-registers as being used.
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void RegScavenger::setUsed(unsigned Reg, bool ImpDef) {
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RegsAvailable.reset(Reg);
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ImplicitDefed[Reg] = ImpDef;
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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RegsAvailable.reset(SubReg);
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ImplicitDefed[SubReg] = ImpDef;
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}
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}
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/// setUnused - Set the register and its sub-registers as being unused.
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void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
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RegsAvailable.set(Reg);
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ImplicitDefed.reset(Reg);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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if (!RedefinesSuperRegPart(MI, Reg, TRI)) {
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RegsAvailable.set(SubReg);
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ImplicitDefed.reset(SubReg);
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}
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}
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void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
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MachineFunction &MF = *mbb->getParent();
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const TargetMachine &TM = MF.getTarget();
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TII = TM.getInstrInfo();
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TRI = TM.getRegisterInfo();
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MRI = &MF.getRegInfo();
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assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
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"Target changed?");
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if (!MBB) {
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NumPhysRegs = TRI->getNumRegs();
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RegsAvailable.resize(NumPhysRegs);
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ImplicitDefed.resize(NumPhysRegs);
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// Create reserved registers bitvector.
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ReservedRegs = TRI->getReservedRegs(MF);
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// Create callee-saved registers bitvector.
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CalleeSavedRegs.resize(NumPhysRegs);
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const unsigned *CSRegs = TRI->getCalleeSavedRegs();
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if (CSRegs != NULL)
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for (unsigned i = 0; CSRegs[i]; ++i)
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CalleeSavedRegs.set(CSRegs[i]);
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}
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MBB = mbb;
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ScavengedReg = 0;
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ScavengedRC = NULL;
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// All registers started out unused.
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RegsAvailable.set();
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// Reserved registers are always used.
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RegsAvailable ^= ReservedRegs;
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// Live-in registers are in use.
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if (!MBB->livein_empty())
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for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
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E = MBB->livein_end(); I != E; ++I)
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setUsed(*I);
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Tracking = false;
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}
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void RegScavenger::restoreScavengedReg() {
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if (!ScavengedReg)
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return;
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TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
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ScavengingFrameIndex, ScavengedRC);
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MachineBasicBlock::iterator II = prior(MBBI);
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TRI->eliminateFrameIndex(II, 0, this);
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setUsed(ScavengedReg);
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ScavengedReg = 0;
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ScavengedRC = NULL;
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}
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/// isLiveInButUnusedBefore - Return true if register is livein the MBB not
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/// not used before it reaches the MI that defines register.
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static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
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MachineBasicBlock *MBB,
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const TargetRegisterInfo *TRI,
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MachineRegisterInfo* MRI) {
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// First check if register is livein.
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bool isLiveIn = false;
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for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
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E = MBB->livein_end(); I != E; ++I)
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if (Reg == *I || TRI->isSuperRegister(Reg, *I)) {
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isLiveIn = true;
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break;
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}
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if (!isLiveIn)
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return false;
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// Is there any use of it before the specified MI?
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SmallPtrSet<MachineInstr*, 4> UsesInMBB;
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for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
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UE = MRI->use_end(); UI != UE; ++UI) {
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MachineInstr *UseMI = &*UI;
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if (UseMI->getParent() == MBB)
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UsesInMBB.insert(UseMI);
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}
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if (UsesInMBB.empty())
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return true;
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I)
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if (UsesInMBB.count(&*I))
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return false;
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return true;
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}
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void RegScavenger::forward() {
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// Move ptr forward.
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if (!Tracking) {
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MBBI = MBB->begin();
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Tracking = true;
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} else {
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assert(MBBI != MBB->end() && "Already at the end of the basic block!");
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MBBI = next(MBBI);
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}
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MachineInstr *MI = MBBI;
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const TargetInstrDesc &TID = MI->getDesc();
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// Reaching a terminator instruction. Restore a scavenged register (which
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// must be life out.
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if (TID.isTerminator())
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restoreScavengedReg();
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// Process uses first.
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BitVector ChangedRegs(NumPhysRegs);
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isRegister() || !MO.isUse())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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if (!isUsed(Reg)) {
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// Register has been scavenged. Restore it!
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if (Reg != ScavengedReg)
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assert(false && "Using an undefined register!");
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else
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restoreScavengedReg();
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}
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if (MO.isKill() && !isReserved(Reg)) {
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ChangedRegs.set(Reg);
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// Mark sub-registers as changed if they aren't defined in the same
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// instruction.
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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ChangedRegs.set(SubReg);
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}
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}
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// Change states of all registers after all the uses are processed to guard
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// against multiple uses.
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setUnused(ChangedRegs);
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// Process defs.
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bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isRegister() || !MO.isDef())
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continue;
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unsigned Reg = MO.getReg();
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// If it's dead upon def, then it is now free.
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if (MO.isDead()) {
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setUnused(Reg, MI);
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continue;
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}
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// Skip two-address destination operand.
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if (TID.findTiedToSrcOperand(i) != -1) {
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assert(isUsed(Reg) && "Using an undefined register!");
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continue;
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}
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// Skip is this is merely redefining part of a super-register.
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if (RedefinesSuperRegPart(MI, MO, TRI))
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continue;
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// Implicit def is allowed to "re-define" any register. Similarly,
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// implicitly defined registers can be clobbered.
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assert((isReserved(Reg) || isUnused(Reg) ||
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IsImpDef || isImplicitlyDefined(Reg) ||
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isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
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"Re-defining a live register!");
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setUsed(Reg, IsImpDef);
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}
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}
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void RegScavenger::backward() {
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assert(Tracking && "Not tracking states!");
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assert(MBBI != MBB->begin() && "Already at start of basic block!");
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// Move ptr backward.
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MBBI = prior(MBBI);
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MachineInstr *MI = MBBI;
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// Process defs first.
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const TargetInstrDesc &TID = MI->getDesc();
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isRegister() || !MO.isDef())
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continue;
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// Skip two-address destination operand.
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if (TID.findTiedToSrcOperand(i) != -1)
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continue;
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unsigned Reg = MO.getReg();
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assert(isUsed(Reg));
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if (!isReserved(Reg))
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setUnused(Reg, MI);
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}
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// Process uses.
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BitVector ChangedRegs(NumPhysRegs);
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isRegister() || !MO.isUse())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0)
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continue;
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assert(isUnused(Reg) || isReserved(Reg));
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ChangedRegs.set(Reg);
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// Set the sub-registers as "used".
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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ChangedRegs.set(SubReg);
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}
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setUsed(ChangedRegs);
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}
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void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
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if (includeReserved)
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used = ~RegsAvailable;
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else
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used = ~RegsAvailable & ~ReservedRegs;
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}
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/// CreateRegClassMask - Set the bits that represent the registers in the
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/// TargetRegisterClass.
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static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
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for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
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++I)
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Mask.set(*I);
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}
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unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
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const BitVector &Candidates) const {
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// Mask off the registers which are not in the TargetRegisterClass.
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BitVector RegsAvailableCopy(NumPhysRegs, false);
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CreateRegClassMask(RegClass, RegsAvailableCopy);
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RegsAvailableCopy &= RegsAvailable;
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// Restrict the search to candidates.
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RegsAvailableCopy &= Candidates;
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// Returns the first unused (bit is set) register, or 0 is none is found.
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int Reg = RegsAvailableCopy.find_first();
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return (Reg == -1) ? 0 : Reg;
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}
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unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
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bool ExCalleeSaved) const {
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// Mask off the registers which are not in the TargetRegisterClass.
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BitVector RegsAvailableCopy(NumPhysRegs, false);
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CreateRegClassMask(RegClass, RegsAvailableCopy);
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RegsAvailableCopy &= RegsAvailable;
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// If looking for a non-callee-saved register, mask off all the callee-saved
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// registers.
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if (ExCalleeSaved)
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RegsAvailableCopy &= ~CalleeSavedRegs;
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// Returns the first unused (bit is set) register, or 0 is none is found.
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int Reg = RegsAvailableCopy.find_first();
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return (Reg == -1) ? 0 : Reg;
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}
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/// calcDistanceToUse - Calculate the distance to the first use of the
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/// specified register.
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static unsigned calcDistanceToUse(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I, unsigned Reg,
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const TargetRegisterInfo *TRI) {
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unsigned Dist = 0;
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I = next(I);
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while (I != MBB->end()) {
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Dist++;
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if (I->readsRegister(Reg, TRI))
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return Dist;
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I = next(I);
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}
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return Dist + 1;
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}
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unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
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MachineBasicBlock::iterator I,
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int SPAdj) {
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assert(ScavengingFrameIndex >= 0 &&
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"Cannot scavenge a register without an emergency spill slot!");
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// Mask off the registers which are not in the TargetRegisterClass.
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BitVector Candidates(NumPhysRegs, false);
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CreateRegClassMask(RC, Candidates);
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Candidates ^= ReservedRegs; // Do not include reserved registers.
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// Exclude all the registers being used by the instruction.
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = I->getOperand(i);
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if (MO.isRegister())
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Candidates.reset(MO.getReg());
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}
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// Find the register whose use is furthest away.
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unsigned SReg = 0;
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unsigned MaxDist = 0;
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int Reg = Candidates.find_first();
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while (Reg != -1) {
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unsigned Dist = calcDistanceToUse(MBB, I, Reg, TRI);
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if (Dist >= MaxDist) {
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MaxDist = Dist;
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SReg = Reg;
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}
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Reg = Candidates.find_next(Reg);
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}
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if (ScavengedReg != 0) {
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// First restore previously scavenged register.
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TII->loadRegFromStackSlot(*MBB, I, ScavengedReg,
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ScavengingFrameIndex, ScavengedRC);
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MachineBasicBlock::iterator II = prior(I);
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TRI->eliminateFrameIndex(II, SPAdj, this);
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}
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TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
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MachineBasicBlock::iterator II = prior(I);
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TRI->eliminateFrameIndex(II, SPAdj, this);
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ScavengedReg = SReg;
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ScavengedRC = RC;
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return SReg;
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}
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