llvm-6502/lib/Target/Sparc
Eric Christopher b7cd35b171 Cache TargetLowering on SelectionDAGISel and update previous
calls to getTargetLowering() with the cached variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219284 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-08 07:32:17 +00:00
..
AsmParser TableGen: allow use of uint64_t for available features mask. 2014-08-18 11:49:42 +00:00
Disassembler
InstPrinter Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
MCTargetDesc Remove HasLEB128. 2014-08-15 14:01:07 +00:00
TargetInfo
CMakeLists.txt Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
DelaySlotFiller.cpp
LLVMBuild.txt
Makefile Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
README.txt JIT support has been added awhile ago. 2014-08-30 14:52:34 +00:00
Sparc.h Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
Sparc.td
SparcAsmPrinter.cpp
SparcCallingConv.td
SparcFrameLowering.cpp
SparcFrameLowering.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcInstr64Bit.td
SparcInstrAliases.td
SparcInstrFormats.td
SparcInstrInfo.cpp Fix a lot of confusion around inserting nops on empty functions. 2014-09-15 18:32:58 +00:00
SparcInstrInfo.h Fix a lot of confusion around inserting nops on empty functions. 2014-09-15 18:32:58 +00:00
SparcInstrInfo.td
SparcInstrVIS.td
SparcISelDAGToDAG.cpp Cache TargetLowering on SelectionDAGISel and update previous 2014-10-08 07:32:17 +00:00
SparcISelLowering.cpp
SparcISelLowering.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcMCInstLower.cpp
SparcRegisterInfo.cpp
SparcRegisterInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcRegisterInfo.td
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcSubtarget.cpp
SparcSubtarget.h Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
SparcTargetMachine.cpp Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
SparcTargetMachine.h Reverting NFC changes from r218050. Instead, the warning was disabled for GCC in r218059, so these changes are no longer required. 2014-09-18 17:34:23 +00:00
SparcTargetObjectFile.cpp
SparcTargetObjectFile.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcTargetStreamer.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.