mirror of
https://github.com/c64scene-ar/llvm-6502.git
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df1c637ac4
the register info for getEncodingValue. This builds on the small patch of yesterday to set HWEncoding in the register file. One (deprecated) use was turned into a hard number to avoid needing register info in the old JIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161628 91177308-0d34-0410-b5e6-96231b3b80d8
422 lines
13 KiB
C++
422 lines
13 KiB
C++
//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the ARM target useful for the compiler back-end and the MC libraries.
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// As such, it deliberately does not include references to LLVM core
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// code gen types, passes, etc..
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMBASEINFO_H
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#define ARMBASEINFO_H
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#include "ARMMCTargetDesc.h"
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#include "llvm/Support/ErrorHandling.h"
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namespace llvm {
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// Enums corresponding to ARM condition codes
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namespace ARMCC {
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// The CondCodes constants map directly to the 4-bit encoding of the
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// condition field for predicated instructions.
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enum CondCodes { // Meaning (integer) Meaning (floating-point)
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EQ, // Equal Equal
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NE, // Not equal Not equal, or unordered
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HS, // Carry set >, ==, or unordered
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LO, // Carry clear Less than
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MI, // Minus, negative Less than
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PL, // Plus, positive or zero >, ==, or unordered
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VS, // Overflow Unordered
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VC, // No overflow Not unordered
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HI, // Unsigned higher Greater than, or unordered
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LS, // Unsigned lower or same Less than or equal
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GE, // Greater than or equal Greater than or equal
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LT, // Less than Less than, or unordered
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GT, // Greater than Greater than
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LE, // Less than or equal <, ==, or unordered
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AL // Always (unconditional) Always (unconditional)
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};
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inline static CondCodes getOppositeCondition(CondCodes CC) {
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switch (CC) {
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default: llvm_unreachable("Unknown condition code");
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case EQ: return NE;
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case NE: return EQ;
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case HS: return LO;
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case LO: return HS;
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case MI: return PL;
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case PL: return MI;
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case VS: return VC;
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case VC: return VS;
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case HI: return LS;
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case LS: return HI;
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case GE: return LT;
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case LT: return GE;
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case GT: return LE;
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case LE: return GT;
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}
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}
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} // namespace ARMCC
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inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
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switch (CC) {
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case ARMCC::EQ: return "eq";
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case ARMCC::NE: return "ne";
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case ARMCC::HS: return "hs";
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case ARMCC::LO: return "lo";
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case ARMCC::MI: return "mi";
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case ARMCC::PL: return "pl";
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case ARMCC::VS: return "vs";
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case ARMCC::VC: return "vc";
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case ARMCC::HI: return "hi";
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case ARMCC::LS: return "ls";
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case ARMCC::GE: return "ge";
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case ARMCC::LT: return "lt";
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case ARMCC::GT: return "gt";
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case ARMCC::LE: return "le";
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case ARMCC::AL: return "al";
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}
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llvm_unreachable("Unknown condition code");
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}
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namespace ARM_PROC {
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enum IMod {
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IE = 2,
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ID = 3
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};
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enum IFlags {
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F = 1,
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I = 2,
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A = 4
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};
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inline static const char *IFlagsToString(unsigned val) {
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switch (val) {
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default: llvm_unreachable("Unknown iflags operand");
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case F: return "f";
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case I: return "i";
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case A: return "a";
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}
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}
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inline static const char *IModToString(unsigned val) {
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switch (val) {
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default: llvm_unreachable("Unknown imod operand");
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case IE: return "ie";
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case ID: return "id";
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}
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}
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}
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namespace ARM_MB {
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// The Memory Barrier Option constants map directly to the 4-bit encoding of
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// the option field for memory barrier operations.
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enum MemBOpt {
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RESERVED_0 = 0,
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RESERVED_1 = 1,
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OSHST = 2,
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OSH = 3,
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RESERVED_4 = 4,
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RESERVED_5 = 5,
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NSHST = 6,
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NSH = 7,
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RESERVED_8 = 8,
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RESERVED_9 = 9,
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ISHST = 10,
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ISH = 11,
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RESERVED_12 = 12,
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RESERVED_13 = 13,
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ST = 14,
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SY = 15
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};
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inline static const char *MemBOptToString(unsigned val) {
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switch (val) {
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default: llvm_unreachable("Unknown memory operation");
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case SY: return "sy";
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case ST: return "st";
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case RESERVED_13: return "#0xd";
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case RESERVED_12: return "#0xc";
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case ISH: return "ish";
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case ISHST: return "ishst";
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case RESERVED_9: return "#0x9";
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case RESERVED_8: return "#0x8";
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case NSH: return "nsh";
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case NSHST: return "nshst";
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case RESERVED_5: return "#0x5";
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case RESERVED_4: return "#0x4";
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case OSH: return "osh";
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case OSHST: return "oshst";
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case RESERVED_1: return "#0x1";
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case RESERVED_0: return "#0x0";
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}
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}
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} // namespace ARM_MB
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/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
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///
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static inline bool isARMLowRegister(unsigned Reg) {
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using namespace ARM;
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switch (Reg) {
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case R0: case R1: case R2: case R3:
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case R4: case R5: case R6: case R7:
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return true;
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default:
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return false;
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}
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}
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/// ARMII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace ARMII {
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/// ARM Index Modes
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enum IndexMode {
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IndexModeNone = 0,
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IndexModePre = 1,
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IndexModePost = 2,
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IndexModeUpd = 3
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};
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/// ARM Addressing Modes
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enum AddrMode {
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AddrModeNone = 0,
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AddrMode1 = 1,
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AddrMode2 = 2,
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AddrMode3 = 3,
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AddrMode4 = 4,
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AddrMode5 = 5,
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AddrMode6 = 6,
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AddrModeT1_1 = 7,
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AddrModeT1_2 = 8,
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AddrModeT1_4 = 9,
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AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
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AddrModeT2_i12 = 11,
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AddrModeT2_i8 = 12,
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AddrModeT2_so = 13,
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AddrModeT2_pc = 14, // +/- i12 for pc relative data
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AddrModeT2_i8s4 = 15, // i8 * 4
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AddrMode_i12 = 16
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};
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inline static const char *AddrModeToString(AddrMode addrmode) {
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switch (addrmode) {
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case AddrModeNone: return "AddrModeNone";
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case AddrMode1: return "AddrMode1";
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case AddrMode2: return "AddrMode2";
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case AddrMode3: return "AddrMode3";
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case AddrMode4: return "AddrMode4";
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case AddrMode5: return "AddrMode5";
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case AddrMode6: return "AddrMode6";
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case AddrModeT1_1: return "AddrModeT1_1";
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case AddrModeT1_2: return "AddrModeT1_2";
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case AddrModeT1_4: return "AddrModeT1_4";
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case AddrModeT1_s: return "AddrModeT1_s";
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case AddrModeT2_i12: return "AddrModeT2_i12";
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case AddrModeT2_i8: return "AddrModeT2_i8";
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case AddrModeT2_so: return "AddrModeT2_so";
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case AddrModeT2_pc: return "AddrModeT2_pc";
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case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
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case AddrMode_i12: return "AddrMode_i12";
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}
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}
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/// Target Operand Flag enum.
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enum TOF {
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//===------------------------------------------------------------------===//
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// ARM Specific MachineOperand flags.
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MO_NO_FLAG,
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/// MO_LO16 - On a symbol operand, this represents a relocation containing
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/// lower 16 bit of the address. Used only via movw instruction.
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MO_LO16,
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/// MO_HI16 - On a symbol operand, this represents a relocation containing
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/// higher 16 bit of the address. Used only via movt instruction.
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MO_HI16,
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/// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
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/// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
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/// i.e. "FOO$non_lazy_ptr".
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/// Used only via movw instruction.
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MO_LO16_NONLAZY,
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/// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
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/// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
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/// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
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MO_HI16_NONLAZY,
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/// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
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/// relocation containing lower 16 bit of the PC relative address of the
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/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
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/// Used only via movw instruction.
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MO_LO16_NONLAZY_PIC,
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/// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
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/// relocation containing lower 16 bit of the PC relative address of the
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/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
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/// Used only via movt instruction.
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MO_HI16_NONLAZY_PIC,
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/// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
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/// call operand.
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MO_PLT
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};
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enum {
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//===------------------------------------------------------------------===//
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// Instruction Flags.
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//===------------------------------------------------------------------===//
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// This four-bit field describes the addressing mode used.
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AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
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// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
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// and store ops only. Generic "updating" flag is used for ld/st multiple.
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// The index mode enums are declared in ARMBaseInfo.h
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IndexModeShift = 5,
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IndexModeMask = 3 << IndexModeShift,
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//===------------------------------------------------------------------===//
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// Instruction encoding formats.
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//
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FormShift = 7,
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FormMask = 0x3f << FormShift,
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// Pseudo instructions
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Pseudo = 0 << FormShift,
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// Multiply instructions
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MulFrm = 1 << FormShift,
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// Branch instructions
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BrFrm = 2 << FormShift,
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BrMiscFrm = 3 << FormShift,
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// Data Processing instructions
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DPFrm = 4 << FormShift,
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DPSoRegFrm = 5 << FormShift,
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// Load and Store
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LdFrm = 6 << FormShift,
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StFrm = 7 << FormShift,
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LdMiscFrm = 8 << FormShift,
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StMiscFrm = 9 << FormShift,
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LdStMulFrm = 10 << FormShift,
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LdStExFrm = 11 << FormShift,
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// Miscellaneous arithmetic instructions
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ArithMiscFrm = 12 << FormShift,
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SatFrm = 13 << FormShift,
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// Extend instructions
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ExtFrm = 14 << FormShift,
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// VFP formats
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VFPUnaryFrm = 15 << FormShift,
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VFPBinaryFrm = 16 << FormShift,
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VFPConv1Frm = 17 << FormShift,
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VFPConv2Frm = 18 << FormShift,
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VFPConv3Frm = 19 << FormShift,
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VFPConv4Frm = 20 << FormShift,
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VFPConv5Frm = 21 << FormShift,
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VFPLdStFrm = 22 << FormShift,
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VFPLdStMulFrm = 23 << FormShift,
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VFPMiscFrm = 24 << FormShift,
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// Thumb format
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ThumbFrm = 25 << FormShift,
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// Miscelleaneous format
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MiscFrm = 26 << FormShift,
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// NEON formats
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NGetLnFrm = 27 << FormShift,
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NSetLnFrm = 28 << FormShift,
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NDupFrm = 29 << FormShift,
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NLdStFrm = 30 << FormShift,
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N1RegModImmFrm= 31 << FormShift,
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N2RegFrm = 32 << FormShift,
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NVCVTFrm = 33 << FormShift,
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NVDupLnFrm = 34 << FormShift,
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N2RegVShLFrm = 35 << FormShift,
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N2RegVShRFrm = 36 << FormShift,
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N3RegFrm = 37 << FormShift,
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N3RegVShFrm = 38 << FormShift,
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NVExtFrm = 39 << FormShift,
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NVMulSLFrm = 40 << FormShift,
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NVTBLFrm = 41 << FormShift,
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//===------------------------------------------------------------------===//
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// Misc flags.
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// UnaryDP - Indicates this is a unary data processing instruction, i.e.
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// it doesn't have a Rn operand.
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UnaryDP = 1 << 13,
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// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
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// a 16-bit Thumb instruction if certain conditions are met.
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Xform16Bit = 1 << 14,
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// ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
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// instruction. Used by the parser to determine whether to require the 'S'
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// suffix on the mnemonic (when not in an IT block) or preclude it (when
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// in an IT block).
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ThumbArithFlagSetting = 1 << 18,
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//===------------------------------------------------------------------===//
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// Code domain.
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DomainShift = 15,
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DomainMask = 7 << DomainShift,
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DomainGeneral = 0 << DomainShift,
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DomainVFP = 1 << DomainShift,
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DomainNEON = 2 << DomainShift,
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DomainNEONA8 = 4 << DomainShift,
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//===------------------------------------------------------------------===//
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// Field shifts - such shifts are used to set field while generating
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// machine instructions.
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//
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// FIXME: This list will need adjusting/fixing as the MC code emitter
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// takes shape and the ARMCodeEmitter.cpp bits go away.
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ShiftTypeShift = 4,
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M_BitShift = 5,
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ShiftImmShift = 5,
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ShiftShift = 7,
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N_BitShift = 7,
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ImmHiShift = 8,
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SoRotImmShift = 8,
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RegRsShift = 8,
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ExtRotImmShift = 10,
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RegRdLoShift = 12,
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RegRdShift = 12,
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RegRdHiShift = 16,
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RegRnShift = 16,
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S_BitShift = 20,
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W_BitShift = 21,
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AM3_I_BitShift = 22,
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D_BitShift = 22,
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U_BitShift = 23,
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P_BitShift = 24,
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I_BitShift = 25,
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CondShift = 28
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};
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} // end namespace ARMII
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} // end namespace llvm;
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#endif
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