Jakob Stoklund Olesen 73ea7bf450 Add the SubRegIndex TableGen class. ... This is the beginning of purely symbolic subregister indices, but we need a bit of jiggling before the explicit numeric indices can be completely removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8		2010-05-24 14:48:12 +00:00
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Mangler.h
SubtargetFeature.h	The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a	2010-05-11 00:30:02 +00:00
Target.td	Add the SubRegIndex TableGen class.	2010-05-24 14:48:12 +00:00
TargetAsmBackend.h	MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can	2010-05-12 00:38:17 +00:00
TargetAsmLexer.h
TargetAsmParser.h
TargetCallingConv.td
TargetData.h
TargetELFWriterInfo.h
TargetFrameInfo.h
TargetInstrDesc.h
TargetInstrInfo.h	Implement @llvm.returnaddress. rdar://8015977.	2010-05-22 01:47:14 +00:00
TargetInstrItineraries.h
TargetIntrinsicInfo.h
TargetJITInfo.h
TargetLowering.h	Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.	2010-05-20 23:26:43 +00:00
TargetLoweringObjectFile.h	Add a new section and accessor for TLS data.	2010-05-22 00:00:58 +00:00
TargetMachine.h	Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.	2010-05-20 23:26:43 +00:00
TargetOpcodes.h	Add a pseudo instruction REG_SEQUENCE that takes a list of registers and	2010-05-01 00:28:44 +00:00
TargetOptions.h	Remove the -enable-sjlj-eh option, which doesn't do anything.	2010-05-02 15:36:26 +00:00
TargetRegisterInfo.h	Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE	2010-05-14 23:21:14 +00:00
TargetRegistry.h	Currently, createMachOStreamer() is invoked directly in llvm-mc which	2010-05-21 12:54:43 +00:00
TargetSchedule.td
TargetSelect.h
TargetSelectionDAG.td
TargetSelectionDAGInfo.h	Fix a comment.	2010-05-11 18:03:41 +00:00
TargetSubtarget.h