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https://github.com/c64scene-ar/llvm-6502.git
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602b9ff595
belong to different register classes easier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4773 91177308-0d34-0410-b5e6-96231b3b80d8
89 lines
2.8 KiB
C++
89 lines
2.8 KiB
C++
//===-- X86RegisterInfo.def - X86 Register Information ----------*- C++ -*-===//
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//
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// This file describes all of the registers that the X86 backend uses. It relies
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// on an external 'R' macro being defined that takes the arguments specified
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// below, and is used to make all of the information relevant to registers be in
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// one place.
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//
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//===----------------------------------------------------------------------===//
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// NOTE: No include guards desired
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#ifndef R
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#errror "Must define R macro before including X86/X86RegisterInfo.def!"
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#endif
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#ifndef R8
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#define R8(ENUM, NAME, FLAGS, TSFLAGS) R(ENUM, NAME, FLAGS, TSFLAGS)
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#endif
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#ifndef R16
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#define R16(ENUM, NAME, FLAGS, TSFLAGS) R(ENUM, NAME, FLAGS, TSFLAGS)
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#endif
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#ifndef R32
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#define R32(ENUM, NAME, FLAGS, TSFLAGS) R(ENUM, NAME, FLAGS, TSFLAGS)
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#endif
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// Arguments passed into the R macro
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// #1: Enum Name - This ends up being a symbol in the X86 namespace
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// #2: Register name - The name of the register as used by the gnu assembler
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// #3: Register Flags - A bitfield of flags or'd together from the
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// MRegisterInfo.h file.
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// #4: Target Specific Flags - Another bitfield containing X86 specific flags
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// as neccesary.
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// The first register must always be a 'noop' register for all backends. This
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// is used as the destination register for instructions that do not produce a
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// value. Some frontends may use this as an operand register to mean special
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// things, for example, the Sparc backend uses R#0 to mean %g0 which always
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// PRODUCES the value 0.
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//
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// The X86 backend uses this value as an operand register only in memory
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// references where it means that there is no base or index register.
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//
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R(NoReg, "none", 0, 0)
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// 32 bit registers, ordered as the processor does...
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R32(EAX, "EAX", MRF::INT32, 0)
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R32(ECX, "ECX", MRF::INT32, 0)
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R32(EDX, "EDX", MRF::INT32, 0)
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R32(EBX, "EBX", MRF::INT32, 0)
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R32(ESP, "ESP", MRF::INT32, 0)
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R32(EBP, "EBP", MRF::INT32, 0)
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R32(ESI, "ESI", MRF::INT32, 0)
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R32(EDI, "EDI", MRF::INT32, 0)
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// 16 bit registers, aliased with the corresponding 32 bit registers above
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R16(AX, "AX", MRF::INT16, 0)
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R16(CX, "CX", MRF::INT16, 0)
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R16(DX, "DX", MRF::INT16, 0)
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R16(BX, "BX", MRF::INT16, 0)
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R16(SP, "SP", MRF::INT16, 0)
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R16(BP, "BP", MRF::INT16, 0)
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R16(SI, "SI", MRF::INT16, 0)
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R16(DI, "DI", MRF::INT16, 0)
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// 8 bit registers aliased with registers above as well
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R8(AL, "AL", MRF::INT8, 0)
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R8(CL, "CL", MRF::INT8, 0)
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R8(DL, "DL", MRF::INT8, 0)
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R8(BL, "BL", MRF::INT8, 0)
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R8(AH, "AH", MRF::INT8, 0)
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R8(CH, "CH", MRF::INT8, 0)
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R8(DH, "DH", MRF::INT8, 0)
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R8(BH, "BH", MRF::INT8, 0)
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// Flags, Segment registers, etc...
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// This is a slimy hack to make it possible to say that flags are clobbered...
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// Ideally we'd model instructions based on which particular flag(s) they
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// could clobber.
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R(EFLAGS, "EFLAGS", MRF::INT16, 0)
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// We are now done with the R* macros
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#undef R
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#undef R8
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#undef R16
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#undef R32
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