llvm-6502/test/CodeGen/AArch64/i128-align.ll
Tim Northover fef8e383eb ARM64: use 32-bit moves for constants where possible.
If we know that a particular 64-bit constant has all high bits zero, then we
can rely on the fact that 32-bit ARM64 instructions automatically zero out the
high bits of an x-register. This gives the expansion logic less constraints to
satisfy and so sometimes allows it to pick better sequences.

Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a
32-bit MOVN to be used in @test8 soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206379 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 11:52:51 +00:00

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810 B
LLVM

; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=arm64-apple-ios7.0 -verify-machineinstrs -o - %s | FileCheck %s
%struct = type { i32, i128, i8 }
@var = global %struct zeroinitializer
define i64 @check_size() {
; CHECK-LABEL: check_size:
%starti = ptrtoint %struct* @var to i64
%endp = getelementptr %struct* @var, i64 1
%endi = ptrtoint %struct* %endp to i64
%diff = sub i64 %endi, %starti
ret i64 %diff
; CHECK: {{movz x0, #48|orr w0, wzr, #0x30}}
}
define i64 @check_field() {
; CHECK-LABEL: check_field:
%starti = ptrtoint %struct* @var to i64
%endp = getelementptr %struct* @var, i64 0, i32 1
%endi = ptrtoint i128* %endp to i64
%diff = sub i64 %endi, %starti
ret i64 %diff
; CHECK: {{movz x0, #16|orr w0, wzr, #0x10}}
}