llvm-6502/test/CodeGen/AArch64/neon-idiv.ll
Benjamin Kramer 43705683fd AArch64: Mark vector long multiplication as expand.
There are no patterns for this. This was already fixed for ARM64 but I forgot
to apply it to AArch64 too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207515 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 09:37:54 +00:00

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390 B
LLVM

; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -mattr=+neon | FileCheck %s
; RUN: llc -mtriple=arm64-none-linux-gnu < %s -mattr=+neon | FileCheck %s
define <4 x i32> @test1(<4 x i32> %a) {
%rem = srem <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
ret <4 x i32> %rem
; CHECK-LABEL: test1
; FIXME: Can we lower this more efficiently?
; CHECK: mul
; CHECK: mul
; CHECK: mul
; CHECK: mul
}