mirror of
https://github.com/c64scene-ar/llvm-6502.git
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419f376564
lib/Target/PowerPC/PPCISelLowering.{h,cpp}
Rename LowerFormalArguments_Darwin to LowerFormalArguments_Darwin_Or_64SVR4.
Rename LowerFormalArguments_SVR4 to LowerFormalArguments_32SVR4.
Receive small structs right-justified in LowerFormalArguments_Darwin_Or_64SVR4.
Rename LowerCall_Darwin to LowerCall_Darwin_Or_64SVR4.
Rename LowerCall_SVR4 to LowerCall_32SVR4.
Pass small structs right-justified in LowerCall_Darwin_Or_64SVR4.
test/CodeGen/PowerPC/structsinregs.ll
New test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164228 91177308-0d34-0410-b5e6-96231b3b80d8
503 lines
22 KiB
C++
503 lines
22 KiB
C++
//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that PPC uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
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#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
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#include "PPC.h"
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#include "PPCSubtarget.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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namespace llvm {
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namespace PPCISD {
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enum NodeType {
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// Start the numbering where the builtin ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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/// FSEL - Traditional three-operand fsel node.
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///
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FSEL,
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/// FCFID - The FCFID instruction, taking an f64 operand and producing
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/// and f64 value containing the FP representation of the integer that
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/// was temporarily in the f64 operand.
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FCFID,
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/// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
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/// operand, producing an f64 value containing the integer representation
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/// of that FP value.
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FCTIDZ, FCTIWZ,
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/// STFIWX - The STFIWX instruction. The first operand is an input token
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/// chain, then an f64 value to store, then an address to store it to.
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STFIWX,
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// VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
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// three v4f32 operands and producing a v4f32 result.
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VMADDFP, VNMSUBFP,
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/// VPERM - The PPC VPERM Instruction.
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///
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VPERM,
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/// Hi/Lo - These represent the high and low 16-bit parts of a global
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/// address respectively. These nodes have two operands, the first of
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/// which must be a TargetGlobalAddress, and the second of which must be a
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/// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
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/// though these are usually folded into other nodes.
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Hi, Lo,
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TOC_ENTRY,
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/// The following three target-specific nodes are used for calls through
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/// function pointers in the 64-bit SVR4 ABI.
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/// Restore the TOC from the TOC save area of the current stack frame.
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/// This is basically a hard coded load instruction which additionally
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/// takes/produces a flag.
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TOC_RESTORE,
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/// Like a regular LOAD but additionally taking/producing a flag.
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LOAD,
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/// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
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/// a hard coded load instruction.
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LOAD_TOC,
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/// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
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/// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
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/// compute an allocation on the stack.
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DYNALLOC,
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/// GlobalBaseReg - On Darwin, this node represents the result of the mflr
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/// at function entry, used for PIC code.
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GlobalBaseReg,
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/// These nodes represent the 32-bit PPC shifts that operate on 6-bit
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/// shift amounts. These nodes are generated by the multi-precision shift
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/// code.
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SRL, SRA, SHL,
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/// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
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/// registers.
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EXTSW_32,
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/// CALL - A direct function call.
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/// CALL_NOP_SVR4 is a call with the special NOP which follows 64-bit
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/// SVR4 calls.
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CALL_Darwin, CALL_SVR4, CALL_NOP_SVR4,
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/// NOP - Special NOP which follows 64-bit SVR4 calls.
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NOP,
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/// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
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/// MTCTR instruction.
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MTCTR,
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/// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
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/// BCTRL instruction.
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BCTRL_Darwin, BCTRL_SVR4,
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/// Return with a flag operand, matched by 'blr'
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RET_FLAG,
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/// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
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/// instructions. This copies the bits corresponding to the specified
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/// CRREG into the resultant GPR. Bits corresponding to other CR regs
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/// are undefined.
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MFCR,
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/// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
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/// instructions. For lack of better number, we use the opcode number
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/// encoding for the OPC field to identify the compare. For example, 838
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/// is VCMPGTSH.
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VCMP,
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/// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
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/// altivec VCMP*o instructions. For lack of better number, we use the
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/// opcode number encoding for the OPC field to identify the compare. For
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/// example, 838 is VCMPGTSH.
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VCMPo,
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/// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
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/// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
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/// condition register to branch on, OPC is the branch opcode to use (e.g.
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/// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
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/// an optional input flag argument.
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COND_BRANCH,
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// The following 5 instructions are used only as part of the
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// long double-to-int conversion sequence.
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/// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
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/// register.
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MFFS,
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/// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
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MTFSB0,
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/// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
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MTFSB1,
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/// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
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/// rounding towards zero. It has flags added so it won't move past the
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/// FPSCR-setting instructions.
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FADDRTZ,
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/// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
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MTFSF,
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/// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
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/// reserve indexed. This is used to implement atomic operations.
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LARX,
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/// STCX = This corresponds to PPC stcx. instrcution: store conditional
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/// indexed. This is used to implement atomic operations.
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STCX,
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/// TC_RETURN - A tail call return.
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/// operand #0 chain
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/// operand #1 callee (register or absolute)
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/// operand #2 stack adjustment
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/// operand #3 optional in flag
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TC_RETURN,
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/// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
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CR6SET,
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CR6UNSET,
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/// STD_32 - This is the STD instruction for use with "32-bit" registers.
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STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
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/// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
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/// byte-swapping store instruction. It byte-swaps the low "Type" bits of
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/// the GPRC input, then stores it through Ptr. Type can be either i16 or
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/// i32.
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STBRX,
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/// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
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/// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
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/// then puts it in the bottom bits of the GPRC. TYPE can be either i16
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/// or i32.
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LBRX
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};
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}
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/// Define some predicates that are used for node matching.
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namespace PPC {
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/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
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/// VPKUHUM instruction.
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bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
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/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
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/// VPKUWUM instruction.
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bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
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/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
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bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
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bool isUnary);
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/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
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bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
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bool isUnary);
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/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
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/// amount, otherwise return -1.
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int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
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/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a splat of a single element that is suitable for input to
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/// VSPLTB/VSPLTH/VSPLTW.
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bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
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/// isAllNegativeZeroVector - Returns true if all elements of build_vector
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/// are -0.0.
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bool isAllNegativeZeroVector(SDNode *N);
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/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
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/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
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unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
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/// get_VSPLTI_elt - If this is a build_vector of constants which can be
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/// formed by using a vspltis[bhw] instruction of the specified element
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/// size, return the constant being splatted. The ByteSize field indicates
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/// the number of bytes of each element [124] -> [bhw].
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SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
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}
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class PPCTargetLowering : public TargetLowering {
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const PPCSubtarget &PPCSubTarget;
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public:
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explicit PPCTargetLowering(PPCTargetMachine &TM);
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/// getTargetNodeName() - This method returns the name of a target specific
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
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/// getSetCCResultType - Return the ISD::SETCC ValueType
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virtual EVT getSetCCResultType(EVT VT) const;
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/// getPreIndexedAddressParts - returns true by value, base pointer and
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/// offset pointer and addressing mode by reference if the node's address
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/// can be legally represented as pre-indexed load / store address.
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virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
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SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const;
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/// SelectAddressRegReg - Given the specified addressed, check to see if it
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/// can be represented as an indexed [r+r] operation. Returns false if it
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/// can be more efficiently represented with [r+imm].
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bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
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SelectionDAG &DAG) const;
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/// SelectAddressRegImm - Returns true if the address N can be represented
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/// by a base register plus a signed 16-bit displacement [r+imm], and if it
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/// is not better represented as reg+reg.
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bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
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SelectionDAG &DAG) const;
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/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
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/// represented as an indexed [r+r] operation.
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bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
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SelectionDAG &DAG) const;
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/// SelectAddressRegImmShift - Returns true if the address N can be
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/// represented by a base register plus a signed 14-bit displacement
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/// [r+imm*4]. Suitable for use by STD and friends.
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bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
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SelectionDAG &DAG) const;
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Sched::Preference getSchedulingPreference(SDNode *N) const;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/// ReplaceNodeResults - Replace the results of node with an illegal result
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/// type with new values built out of custom code.
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///
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virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual void computeMaskedBitsForTargetNode(const SDValue Op,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
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MachineBasicBlock *MBB, bool is64Bit,
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unsigned BinOpcode) const;
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MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
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MachineBasicBlock *MBB,
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bool is8bit, unsigned Opcode) const;
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ConstraintType getConstraintType(const std::string &Constraint) const;
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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ConstraintWeight getSingleConstraintMatchWeight(
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AsmOperandInfo &info, const char *constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const;
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/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
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/// function arguments in the caller parameter area. This is the actual
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/// alignment, not its logarithm.
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unsigned getByValTypeAlignment(Type *Ty) const;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops.
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virtual void LowerAsmOperandForConstraint(SDValue Op,
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std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
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/// isLegalAddressImmediate - Return true if the integer value can be used
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/// as the offset of the target addressing mode for load / store of the
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/// given type.
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virtual bool isLegalAddressImmediate(int64_t V, Type *Ty) const;
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/// isLegalAddressImmediate - Return true if the GlobalValue can be used as
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/// the offset of the target addressing mode.
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virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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/// getOptimalMemOpType - Returns the target specific optimal type for load
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/// and store operations as a result of memset, memcpy, and memmove
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/// lowering. If DstAlign is zero that means it's safe to destination
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/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
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/// means there isn't a need to check it against alignment requirement,
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/// probably because the source does not need to be loaded. If
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/// 'IsZeroVal' is true, that means it's safe to return a
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/// non-scalar-integer type, e.g. empty string source, constant, or loaded
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/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
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/// constant so it does not need to be loaded.
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/// It returns EVT::Other if the type should be determined using generic
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/// target-independent logic.
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virtual EVT
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getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
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bool IsZeroVal, bool MemcpyStrSrc,
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MachineFunction &MF) const;
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/// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
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/// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
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/// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
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/// is expanded to mul + add.
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virtual bool isFMAFasterThanMulAndAdd(EVT VT) const;
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private:
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SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
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SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
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bool
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IsEligibleForTailCallOptimization(SDValue Callee,
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CallingConv::ID CalleeCC,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SelectionDAG& DAG) const;
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SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
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int SPDiff,
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SDValue Chain,
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SDValue &LROpOut,
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SDValue &FPOpOut,
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bool isDarwinABI,
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DebugLoc dl) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
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const PPCSubtarget &Subtarget) const;
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SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
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const PPCSubtarget &Subtarget) const;
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SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
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const PPCSubtarget &Subtarget) const;
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
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const PPCSubtarget &Subtarget) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const;
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SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
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bool isVarArg,
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SelectionDAG &DAG,
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SmallVector<std::pair<unsigned, SDValue>, 8>
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&RegsToPass,
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SDValue InFlag, SDValue Chain,
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SDValue &Callee,
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int SPDiff, unsigned NumBytes,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SmallVectorImpl<SDValue> &InVals) const;
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|
|
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
|
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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|
|
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virtual SDValue
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LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
virtual bool
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CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
|
|
bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
LLVMContext &Context) const;
|
|
|
|
virtual SDValue
|
|
LowerReturn(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
DebugLoc dl, SelectionDAG &DAG) const;
|
|
|
|
SDValue
|
|
LowerFormalArguments_Darwin_Or_64SVR4(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
SDValue
|
|
LowerFormalArguments_32SVR4(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
SDValue
|
|
LowerCall_Darwin_Or_64SVR4(SDValue Chain, SDValue Callee,
|
|
CallingConv::ID CallConv,
|
|
bool isVarArg, bool isTailCall,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
SDValue
|
|
LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
|
bool isVarArg, bool isTailCall,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
};
|
|
}
|
|
|
|
#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
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