Preston Gurd 1fd36e41e4 This patch follows is a follow up to r178171, which uses the register ... form of call in preference to memory indirect on Atom. In this case, the patch applies the optimization to the code for reloading spilled registers. The patch also includes changes to sibcall.ll and movgs.ll, which were failing on the Atom buildbot after the first patch was applied. This patch by Sriram Murali. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178193 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-27 23:16:18 +00:00
..
AArch64	Update PEI's virtual-register-based scavenging to support multiple simultaneous mappings	2013-03-26 18:56:54 +00:00
ARM	Enabling the generation of dependency breakers for partial updates on Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32.	2013-03-27 12:38:44 +00:00
CPP
Generic	XFAIL some of the generic CodeGen tests for Hexagon.	2013-03-25 21:04:16 +00:00
Hexagon	Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.	2013-03-26 15:43:57 +00:00
Inputs	Adding DIImportedModules to DIScopes.	2013-03-27 00:07:26 +00:00
MBlaze
Mips
MSP430
NVPTX	[NVPTX] Fix handling of vector arguments	2013-03-24 21:17:47 +00:00
PowerPC	Print PPC ZERO as 0 (not r0) even on Darwin	2013-03-27 13:20:52 +00:00
R600	R600/SI: add SETO/SETUO patterns	2013-03-27 15:27:31 +00:00
SI
SPARC
Thumb	Adding DIImportedModules to DIScopes.	2013-03-27 00:07:26 +00:00
Thumb2
X86	This patch follows is a follow up to r178171, which uses the register	2013-03-27 23:16:18 +00:00
XCore