llvm-6502/test/CodeGen/ARM/data-in-code-annotations.ll
Tim Northover d0dbe02fd2 ARM & AArch64: make use of common cmpxchg idioms after expansion
The C and C++ semantics for compare_exchange require it to return a bool
indicating success. This gets mapped to LLVM IR which follows each cmpxchg with
an icmp of the value loaded against the desired value.

When lowered to ldxr/stxr loops, this extra comparison is redundant: its
results are implicit in the control-flow of the function.

This commit makes two changes: it replaces that icmp with appropriate PHI
nodes, and then makes sure earlyCSE is called after expansion to actually make
use of the opportunities revealed.

I've also added -{arm,aarch64}-enable-atomic-tidy options, so that
existing fragile tests aren't perturbed too much by the change. Many
of them either rely on undef/unreachable too pervasively to be
restored to something well-defined (particularly while making sure
they test the same obscure assert from many years ago), or depend on a
particular CFG shape, which is disrupted by SimplifyCFG.

rdar://problem/16227836

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209883 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-30 10:09:59 +00:00

43 lines
1.1 KiB
LLVM

; RUN: llc < %s -mtriple=armv7-apple-darwin -arm-atomic-cfg-tidy=0 | FileCheck %s
define double @f1() nounwind {
; CHECK-LABEL: f1:
; CHECK: .data_region
; CHECK: .long 1413754129
; CHECK: .long 1074340347
; CHECK: .end_data_region
ret double 0x400921FB54442D11
}
define i32 @f2() {
; CHECK-LABEL: f2:
; CHECK: .data_region jt32
; CHECK: .end_data_region
entry:
switch i32 undef, label %return [
i32 1, label %sw.bb
i32 2, label %sw.bb6
i32 3, label %sw.bb13
i32 4, label %sw.bb20
]
sw.bb: ; preds = %entry
br label %return
sw.bb6: ; preds = %entry
br label %return
sw.bb13: ; preds = %entry
br label %return
sw.bb20: ; preds = %entry
%div = sdiv i32 undef, undef
br label %return
return: ; preds = %sw.bb20, %sw.bb13, %sw.bb6, %sw.bb, %entry
%retval.0 = phi i32 [ %div, %sw.bb20 ], [ undef, %sw.bb13 ], [ undef, %sw.bb6 ], [ undef, %sw.bb ], [ 0, %entry ]
ret i32 %retval.0
}