mirror of
https://github.com/c64scene-ar/llvm-6502.git
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28c2fda9df
Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234486 91177308-0d34-0410-b5e6-96231b3b80d8
53 lines
1.3 KiB
LLVM
53 lines
1.3 KiB
LLVM
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-SWDIV
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; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-HWDIV
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; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4 | FileCheck %s -check-prefix=CHECK-SWDIV
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; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f | FileCheck %s -check-prefix=CHECK-SWDIV
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; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV
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define i32 @f1(i32 %a, i32 %b) {
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entry:
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; CHECK-SWDIV: f1
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; CHECK-SWDIV: __divsi3
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; CHECK-HWDIV: f1
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; CHECK-HWDIV: sdiv
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%tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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define i32 @f2(i32 %a, i32 %b) {
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entry:
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; CHECK-SWDIV: f2
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; CHECK-SWDIV: __udivsi3
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; CHECK-HWDIV: f2
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; CHECK-HWDIV: udiv
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%tmp1 = udiv i32 %a, %b ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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define i32 @f3(i32 %a, i32 %b) {
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entry:
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; CHECK-SWDIV: f3
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; CHECK-SWDIV: __modsi3
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; CHECK-HWDIV: f3
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; CHECK-HWDIV: sdiv
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; CHECK-HWDIV: mls
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%tmp1 = srem i32 %a, %b ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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define i32 @f4(i32 %a, i32 %b) {
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entry:
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; CHECK-SWDIV: f4
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; CHECK-SWDIV: __umodsi3
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; CHECK-HWDIV: f4
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; CHECK-HWDIV: udiv
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; CHECK-HWDIV: mls
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%tmp1 = urem i32 %a, %b ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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