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https://github.com/c64scene-ar/llvm-6502.git
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49683f3c96
The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
70 lines
1.6 KiB
LLVM
70 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
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;; i8
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define void @st_global_i8(i8 addrspace(0)* %ptr, i8 %a) {
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; PTX32: st.u8 [%r{{[0-9]+}}], %rc{{[0-9]+}}
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; PTX32: ret
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; PTX64: st.u8 [%rl{{[0-9]+}}], %rc{{[0-9]+}}
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; PTX64: ret
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store i8 %a, i8 addrspace(0)* %ptr
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ret void
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}
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;; i16
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define void @st_global_i16(i16 addrspace(0)* %ptr, i16 %a) {
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; PTX32: st.u16 [%r{{[0-9]+}}], %rs{{[0-9]+}}
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; PTX32: ret
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; PTX64: st.u16 [%rl{{[0-9]+}}], %rs{{[0-9]+}}
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; PTX64: ret
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store i16 %a, i16 addrspace(0)* %ptr
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ret void
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}
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;; i32
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define void @st_global_i32(i32 addrspace(0)* %ptr, i32 %a) {
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; PTX32: st.u32 [%r{{[0-9]+}}], %r{{[0-9]+}}
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; PTX32: ret
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; PTX64: st.u32 [%rl{{[0-9]+}}], %r{{[0-9]+}}
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; PTX64: ret
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store i32 %a, i32 addrspace(0)* %ptr
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ret void
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}
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;; i64
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define void @st_global_i64(i64 addrspace(0)* %ptr, i64 %a) {
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; PTX32: st.u64 [%r{{[0-9]+}}], %rl{{[0-9]+}}
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; PTX32: ret
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; PTX64: st.u64 [%rl{{[0-9]+}}], %rl{{[0-9]+}}
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; PTX64: ret
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store i64 %a, i64 addrspace(0)* %ptr
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ret void
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}
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;; f32
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define void @st_global_f32(float addrspace(0)* %ptr, float %a) {
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; PTX32: st.f32 [%r{{[0-9]+}}], %f{{[0-9]+}}
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; PTX32: ret
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; PTX64: st.f32 [%rl{{[0-9]+}}], %f{{[0-9]+}}
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; PTX64: ret
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store float %a, float addrspace(0)* %ptr
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ret void
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}
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;; f64
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define void @st_global_f64(double addrspace(0)* %ptr, double %a) {
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; PTX32: st.f64 [%r{{[0-9]+}}], %fl{{[0-9]+}}
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; PTX32: ret
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; PTX64: st.f64 [%rl{{[0-9]+}}], %fl{{[0-9]+}}
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; PTX64: ret
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store double %a, double addrspace(0)* %ptr
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ret void
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}
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