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https://github.com/c64scene-ar/llvm-6502.git
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8dd26253f5
Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
24 lines
735 B
LLVM
24 lines
735 B
LLVM
; RUN: llc < %s -O0 -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s
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; PR4684
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target datalayout =
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"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-apple-darwin9.8"
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declare void @func2(x86_mmx)
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define void @func1() nounwind {
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; This isn't spectacular, but it's MMX code at -O0...
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; CHECK: movq2dq %mm0, %xmm0
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; For now, handling of x86_mmx parameters in fast Isel is unimplemented,
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; so we get pretty poor code. The below is preferable.
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; CHEK: movl $2, %eax
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; CHEK: movd %rax, %mm0
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; CHEK: movd %mm0, %rdi
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%tmp0 = bitcast <2 x i32><i32 0, i32 2> to x86_mmx
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call void @func2(x86_mmx %tmp0)
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ret void
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}
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