Oliver Stannard d75e7ad0c8 [Thumb2] LDRS?[BH] cannot load to the PC ... The Thumb2 LDRS?[BH] instructions are not valid when the destination register is the PC (these encodings are used for preload hints). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220278 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-21 09:14:15 +00:00
..
AArch64	[AArch64] Allow access to all system registers with MRS/MSR instructions.	2014-10-01 10:13:59 +00:00
ARM	[Thumb2] LDRS?[BH] cannot load to the PC	2014-10-21 09:14:15 +00:00
AsmParser
COFF	MC, COFF: Make bigobj test compatible with python3	2014-10-14 22:35:11 +00:00
Disassembler	[X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit mode for certain instructions it shouldn't.	2014-10-07 07:29:50 +00:00
ELF	Add back commits r219835 and a fixed version of r219829.	2014-10-17 01:48:58 +00:00
MachO	MachObjectWriter: optimize the string table for common suffices	2014-10-06 17:05:19 +00:00
Markup
Mips	[mips][microMIPS] Implement ADDU16 and SUBU16 instructions	2014-10-21 08:44:58 +00:00
PowerPC	[PPC64] VSX indexed-form loads use wrong instruction format	2014-10-09 17:51:35 +00:00
Sparc
SystemZ	Exclude known and bugzilled failures from UBSan bootstrap	2014-09-17 20:17:52 +00:00
X86	[AVX512] Add DQ subvector inserts	2014-10-15 23:42:17 +00:00