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d76eeb1bce
Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3668 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208576 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
964 B
TableGen
35 lines
964 B
TableGen
//=- Mips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips32r6 instruction formats.
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//
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//===----------------------------------------------------------------------===//
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class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
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PredicateControl {
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let DecoderNamespace = "Mips32r6_64r6";
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let EncodingPredicates = [HasStdEnc];
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}
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class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b00000;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = mulop;
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let Inst{5-0} = funct;
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}
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