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https://github.com/c64scene-ar/llvm-6502.git
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d77a7669ec
The input to an RxSBG operation can be narrower as long as the upper bits are don't care. This fixes a FIXME added in r192783. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192790 91177308-0d34-0410-b5e6-96231b3b80d8
67 lines
1.6 KiB
LLVM
67 lines
1.6 KiB
LLVM
; Test compound shifts.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test a shift right followed by a sign extension. This can use two shifts.
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define i64 @f1(i32 %a) {
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; CHECK-LABEL: f1:
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; CHECK: sllg [[REG:%r[0-5]]], %r2, 62
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; CHECK: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%shr = lshr i32 %a, 1
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%trunc = trunc i32 %shr to i1
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%ext = sext i1 %trunc to i64
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ret i64 %ext
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}
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; ...and again with the highest shift count.
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define i64 @f2(i32 %a) {
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; CHECK-LABEL: f2:
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; CHECK: sllg [[REG:%r[0-5]]], %r2, 32
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; CHECK: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%shr = lshr i32 %a, 31
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%trunc = trunc i32 %shr to i1
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%ext = sext i1 %trunc to i64
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ret i64 %ext
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}
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; Test a left shift that of an extended right shift in a case where folding
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; is possible.
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define i64 @f3(i32 %a) {
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; CHECK-LABEL: f3:
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; CHECK: risbg %r2, %r2, 27, 181, 9
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; CHECK: br %r14
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%shr = lshr i32 %a, 1
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%ext = zext i32 %shr to i64
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%shl = shl i64 %ext, 10
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%and = and i64 %shl, 137438952960
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ret i64 %and
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}
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; ...and again with a larger right shift.
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define i64 @f4(i32 %a) {
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; CHECK-LABEL: f4:
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; CHECK: risbg %r2, %r2, 30, 158, 3
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; CHECK: br %r14
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%shr = lshr i32 %a, 30
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%ext = sext i32 %shr to i64
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%shl = shl i64 %ext, 33
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%and = and i64 %shl, 8589934592
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ret i64 %and
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}
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; Repeat the previous test in a case where all bits outside the
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; bottom 3 matter.
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define i64 @f5(i32 %a) {
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; CHECK-LABEL: f5:
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; CHECK: risbg %r2, %r2, 29, 158, 3
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; CHECK: lhi %r2, 7
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; CHECK: br %r14
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%shr = lshr i32 %a, 30
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%ext = sext i32 %shr to i64
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%shl = shl i64 %ext, 33
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%or = or i64 %shl, 7
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ret i64 %or
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}
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