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https://github.com/c64scene-ar/llvm-6502.git
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d7802bf0dd
on 64-bit PowerPC ELF. The patch includes code to handle external assembly and MC output with the integrated assembler. It intentionally does not support the "old" JIT. For the initial-exec TLS model, the ABI requires the following to calculate the address of external thread-local variable x: Code sequence Relocation Symbol ld 9,x@got@tprel(2) R_PPC64_GOT_TPREL16_DS x add 9,9,x@tls R_PPC64_TLS x The register 9 is arbitrary here. The linker will replace x@got@tprel with the offset relative to the thread pointer to the generated GOT entry for symbol x. It will replace x@tls with the thread-pointer register (13). The two test cases verify correct assembly output and relocation output as just described. PowerPC-specific selection node variants are added for the two instructions above: LD_GOT_TPREL and ADD_TLS. These are inserted when an initial-exec global variable is encountered by PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to machine instructions LDgotTPREL and ADD8TLS. LDgotTPREL is a pseudo that uses the same LDrs support added for medium code model's LDtocL, with a different relocation type. The rest of the processing is straightforward. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169281 91177308-0d34-0410-b5e6-96231b3b80d8
59 lines
1.5 KiB
C++
59 lines
1.5 KiB
C++
//===-- PPCFixupKinds.h - PPC Specific Fixup Entries ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_PPC_PPCFIXUPKINDS_H
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#define LLVM_PPC_PPCFIXUPKINDS_H
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#include "llvm/MC/MCFixup.h"
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namespace llvm {
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namespace PPC {
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enum Fixups {
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// fixup_ppc_br24 - 24-bit PC relative relocation for direct branches like 'b'
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// and 'bl'.
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fixup_ppc_br24 = FirstTargetFixupKind,
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/// fixup_ppc_brcond14 - 14-bit PC relative relocation for conditional
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/// branches.
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fixup_ppc_brcond14,
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/// fixup_ppc_lo16 - A 16-bit fixup corresponding to lo16(_foo) for instrs
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/// like 'li'.
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fixup_ppc_lo16,
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/// fixup_ppc_ha16 - A 16-bit fixup corresponding to ha16(_foo) for instrs
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/// like 'lis'.
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fixup_ppc_ha16,
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/// fixup_ppc_lo14 - A 14-bit fixup corresponding to lo16(_foo) for instrs
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/// like 'std'.
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fixup_ppc_lo14,
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/// fixup_ppc_toc - Insert value of TOC base (.TOC.).
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fixup_ppc_toc,
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/// fixup_ppc_toc16 - A 16-bit signed fixup relative to the TOC base.
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fixup_ppc_toc16,
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/// fixup_ppc_toc16_ds - A 14-bit signed fixup relative to the TOC base with
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/// implied 2 zero bits
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fixup_ppc_toc16_ds,
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/// fixup_ppc_tlsreg - Insert thread-pointer register number.
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fixup_ppc_tlsreg,
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// Marker
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LastTargetFixupKind,
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NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
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};
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}
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}
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#endif
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