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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
85 lines
3.4 KiB
C++
85 lines
3.4 KiB
C++
//===- SPUInstrInfo.h - Cell SPU Instruction Information --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the CellSPU implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPU_INSTRUCTIONINFO_H
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#define SPU_INSTRUCTIONINFO_H
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#include "SPU.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "SPURegisterInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "SPUGenInstrInfo.inc"
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namespace llvm {
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//! Cell SPU instruction information class
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class SPUInstrInfo : public SPUGenInstrInfo {
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SPUTargetMachine &TM;
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const SPURegisterInfo RI;
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public:
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explicit SPUInstrInfo(SPUTargetMachine &tm);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
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ScheduleHazardRecognizer *
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CreateTargetHazardRecognizer(const TargetMachine *TM,
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const ScheduleDAG *DAG) const;
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unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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//! Store a register to a stack slot, based on its register class.
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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//! Load a register from a stack slot, based on its register class.
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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//! Reverses a branch's condition, returning false on success.
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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};
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}
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#endif
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