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https://github.com/c64scene-ar/llvm-6502.git
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3889a2cb05
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6842 91177308-0d34-0410-b5e6-96231b3b80d8
737 lines
27 KiB
C++
737 lines
27 KiB
C++
//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
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//
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// This file contains the declaration of the MachineInstr class, which is the
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// basic representation for all target dependant machine instructions used by
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// the back end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEINSTR_H
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#define LLVM_CODEGEN_MACHINEINSTR_H
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#include "llvm/Target/MRegisterInfo.h"
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#include "Support/Annotation.h"
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#include "Support/iterator"
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#include <set>
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class Value;
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class Function;
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class MachineBasicBlock;
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class TargetMachine;
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class GlobalValue;
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typedef int MachineOpCode;
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//===----------------------------------------------------------------------===//
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/// Special flags on instructions that modify the opcode.
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/// These flags are unused for now, but having them enforces that some
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/// changes will be needed if they are used.
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///
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enum MachineOpCodeFlags {
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AnnulFlag, /// 1 if annul bit is set on a branch
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PredTakenFlag, /// 1 if branch should be predicted taken
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PredNotTakenFlag /// 1 if branch should be predicted not taken
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};
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//===----------------------------------------------------------------------===//
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/// MOTy - MachineOperandType - This namespace contains an enum that describes
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/// how the machine operand is used by the instruction: is it read, defined, or
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/// both? Note that the MachineInstr/Operator class currently uses bool
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/// arguments to represent this information instead of an enum. Eventually this
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/// should change over to use this _easier to read_ representation instead.
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///
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namespace MOTy {
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enum UseType {
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Use, /// This machine operand is only read by the instruction
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Def, /// This machine operand is only written by the instruction
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UseAndDef /// This machine operand is read AND written
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};
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}
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//===----------------------------------------------------------------------===//
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// class MachineOperand
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//
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// Purpose:
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// Representation of each machine instruction operand.
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// This class is designed so that you can allocate a vector of operands
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// first and initialize each one later.
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//
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// E.g, for this VM instruction:
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// ptr = alloca type, numElements
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// we generate 2 machine instructions on the SPARC:
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//
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// mul Constant, Numelements -> Reg
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// add %sp, Reg -> Ptr
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//
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// Each instruction has 3 operands, listed above. Of those:
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// - Reg, NumElements, and Ptr are of operand type MO_Register.
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// - Constant is of operand type MO_SignExtendedImmed on the SPARC.
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//
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// For the register operands, the virtual register type is as follows:
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//
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// - Reg will be of virtual register type MO_MInstrVirtualReg. The field
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// MachineInstr* minstr will point to the instruction that computes reg.
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//
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// - %sp will be of virtual register type MO_MachineReg.
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// The field regNum identifies the machine register.
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//
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// - NumElements will be of virtual register type MO_VirtualReg.
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// The field Value* value identifies the value.
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//
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// - Ptr will also be of virtual register type MO_VirtualReg.
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// Again, the field Value* value identifies the value.
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//
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//===----------------------------------------------------------------------===//
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struct MachineOperand {
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enum MachineOperandType {
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MO_VirtualRegister, // virtual register for *value
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MO_MachineRegister, // pre-assigned machine register `regNum'
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MO_CCRegister,
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MO_SignExtendedImmed,
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MO_UnextendedImmed,
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MO_PCRelativeDisp,
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MO_MachineBasicBlock, // MachineBasicBlock reference
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MO_FrameIndex, // Abstract Stack Frame Index
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MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
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MO_ExternalSymbol, // Name of external global symbol
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MO_GlobalAddress, // Address of a global value
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};
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private:
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// Bit fields of the flags variable used for different operand properties
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enum {
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DEFONLYFLAG = 0x01, // this is a def but not a use of the operand
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DEFUSEFLAG = 0x02, // this is both a def and a use
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HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
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LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
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HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
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LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
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PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
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USEDEFMASK = 0x03,
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};
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private:
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union {
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Value* value; // BasicBlockVal for a label operand.
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// ConstantVal for a non-address immediate.
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// Virtual register for an SSA operand,
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// including hidden operands required for
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// the generated machine code.
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// LLVM global for MO_GlobalAddress.
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int64_t immedVal; // Constant value for an explicit constant
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MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
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std::string *SymbolName; // For MO_ExternalSymbol type
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};
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char flags; // see bit field definitions above
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MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
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int regNum; // register number for an explicit register
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// will be set for a value after reg allocation
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private:
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MachineOperand()
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: immedVal(0),
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flags(0),
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opType(MO_VirtualRegister),
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regNum(-1) {}
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MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
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: immedVal(ImmVal),
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flags(0),
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opType(OpTy),
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regNum(-1) {}
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MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
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: immedVal(0),
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opType(OpTy),
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regNum(Reg) {
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switch (UseTy) {
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case MOTy::Use: flags = 0; break;
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case MOTy::Def: flags = DEFONLYFLAG; break;
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case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
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default: assert(0 && "Invalid value for UseTy!");
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}
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}
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MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
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bool isPCRelative = false)
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: value(V), opType(OpTy), regNum(-1) {
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switch (UseTy) {
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case MOTy::Use: flags = 0; break;
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case MOTy::Def: flags = DEFONLYFLAG; break;
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case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
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default: assert(0 && "Invalid value for UseTy!");
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}
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if (isPCRelative) flags |= PCRELATIVE;
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}
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MachineOperand(MachineBasicBlock *mbb)
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: MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
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MachineOperand(const std::string &SymName, bool isPCRelative)
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: SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
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opType(MO_ExternalSymbol), regNum(-1) {}
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public:
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MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
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flags(M.flags),
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opType(M.opType),
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regNum(M.regNum) {
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if (isExternalSymbol())
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SymbolName = new std::string(M.getSymbolName());
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}
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~MachineOperand() {
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if (isExternalSymbol())
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delete SymbolName;
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}
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const MachineOperand &operator=(const MachineOperand &MO) {
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immedVal = MO.immedVal;
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flags = MO.flags;
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opType = MO.opType;
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regNum = MO.regNum;
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if (isExternalSymbol())
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SymbolName = new std::string(MO.getSymbolName());
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return *this;
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}
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// Accessor methods. Caller is responsible for checking the
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// operand type before invoking the corresponding accessor.
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//
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MachineOperandType getType() const { return opType; }
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/// isPCRelative - This returns the value of the PCRELATIVE flag, which
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/// indicates whether this operand should be emitted as a PC relative value
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/// instead of a global address. This is used for operands of the forms:
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/// MachineBasicBlock, GlobalAddress, ExternalSymbol
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///
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bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
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// This is to finally stop caring whether we have a virtual or machine
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// register -- an easier interface is to simply call both virtual and machine
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// registers essentially the same, yet be able to distinguish when
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// necessary. Thus the instruction selector can just add registers without
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// abandon, and the register allocator won't be confused.
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bool isVirtualRegister() const {
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return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
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&& regNum >= MRegisterInfo::FirstVirtualRegister;
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}
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bool isPhysicalRegister() const {
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return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
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&& (unsigned)regNum < MRegisterInfo::FirstVirtualRegister;
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}
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bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
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bool isMachineRegister() const { return !isVirtualRegister(); }
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bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
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bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
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bool isImmediate() const {
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return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
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}
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bool isFrameIndex() const { return opType == MO_FrameIndex; }
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bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
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bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
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bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
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Value* getVRegValue() const {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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isPCRelativeDisp());
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return value;
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}
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Value* getVRegValueOrNull() const {
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return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
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isPCRelativeDisp()) ? value : NULL;
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}
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int getMachineRegNum() const {
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assert(opType == MO_MachineRegister);
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return regNum;
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}
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int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
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MachineBasicBlock *getMachineBasicBlock() const {
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assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
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return MBB;
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}
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int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
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unsigned getConstantPoolIndex() const {
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assert(isConstantPoolIndex());
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return immedVal;
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}
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GlobalValue *getGlobal() const {
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assert(isGlobalAddress());
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return (GlobalValue*)value;
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}
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const std::string &getSymbolName() const {
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assert(isExternalSymbol());
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return *SymbolName;
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}
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bool opIsUse () const { return (flags & USEDEFMASK) == 0; }
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bool opIsDefOnly () const { return flags & DEFONLYFLAG; }
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bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
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bool opHiBits32 () const { return flags & HIFLAG32; }
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bool opLoBits32 () const { return flags & LOFLAG32; }
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bool opHiBits64 () const { return flags & HIFLAG64; }
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bool opLoBits64 () const { return flags & LOFLAG64; }
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// used to check if a machine register has been allocated to this operand
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bool hasAllocatedReg() const {
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return (regNum >= 0 &&
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(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister));
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}
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// used to get the reg number if when one is allocated
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int getAllocatedRegNum() const {
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assert(hasAllocatedReg());
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return regNum;
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}
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// ********** TODO: get rid of this duplicate code! ***********
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unsigned getReg() const {
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return getAllocatedRegNum();
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}
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friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
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private:
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// Construction methods needed for fine-grain control.
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// These must be accessed via coresponding methods in MachineInstr.
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void markHi32() { flags |= HIFLAG32; }
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void markLo32() { flags |= LOFLAG32; }
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void markHi64() { flags |= HIFLAG64; }
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void markLo64() { flags |= LOFLAG64; }
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// Replaces the Value with its corresponding physical register after
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// register allocation is complete
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void setRegForValue(int reg) {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister);
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regNum = reg;
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}
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friend class MachineInstr;
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};
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//===----------------------------------------------------------------------===//
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// class MachineInstr
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//
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// Purpose:
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// Representation of each machine instruction.
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//
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// MachineOpCode must be an enum, defined separately for each target.
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// E.g., It is defined in SparcInstructionSelection.h for the SPARC.
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//
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// There are 2 kinds of operands:
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//
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// (1) Explicit operands of the machine instruction in vector operands[]
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//
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// (2) "Implicit operands" are values implicitly used or defined by the
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// machine instruction, such as arguments to a CALL, return value of
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// a CALL (if any), and return value of a RETURN.
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//===----------------------------------------------------------------------===//
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class MachineInstr {
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int opCode; // the opcode
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unsigned opCodeFlags; // flags modifying instrn behavior
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std::vector<MachineOperand> operands; // the operands
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unsigned numImplicitRefs; // number of implicit operands
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// regsUsed - all machine registers used for this instruction, including regs
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// used to save values across the instruction. This is a bitset of registers.
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std::set<int> regsUsed;
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// OperandComplete - Return true if it's illegal to add a new operand
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bool OperandsComplete() const;
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MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT
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void operator=(const MachineInstr&); // DO NOT IMPLEMENT
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public:
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MachineInstr(int Opcode, unsigned numOperands);
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/// MachineInstr ctor - This constructor only does a _reserve_ of the
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/// operands, not a resize for them. It is expected that if you use this that
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/// you call add* methods below to fill up the operands, instead of the Set
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/// methods. Eventually, the "resizing" ctors will be phased out.
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///
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MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY);
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/// MachineInstr ctor - Work exactly the same as the ctor above, except that
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/// the MachineInstr is created and added to the end of the specified basic
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/// block.
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///
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MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps);
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// The opcode.
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//
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const int getOpcode() const { return opCode; }
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const int getOpCode() const { return opCode; }
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// Opcode flags.
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//
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unsigned getOpCodeFlags() const { return opCodeFlags; }
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//
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// Access to explicit operands of the instruction
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//
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unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
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const MachineOperand& getOperand(unsigned i) const {
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assert(i < getNumOperands() && "getOperand() out of range!");
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return operands[i];
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}
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MachineOperand& getOperand(unsigned i) {
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assert(i < getNumOperands() && "getOperand() out of range!");
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return operands[i];
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}
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//
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// Access to explicit or implicit operands of the instruction
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// This returns the i'th entry in the operand vector.
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// That represents the i'th explicit operand or the (i-N)'th implicit operand,
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// depending on whether i < N or i >= N.
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//
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const MachineOperand& getExplOrImplOperand(unsigned i) const {
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assert(i < operands.size() && "getExplOrImplOperand() out of range!");
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return (i < getNumOperands()? getOperand(i)
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: getImplicitOp(i - getNumOperands()));
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}
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//
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// Access to implicit operands of the instruction
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//
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unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
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MachineOperand& getImplicitOp(unsigned i) {
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assert(i < numImplicitRefs && "implicit ref# out of range!");
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return operands[i + operands.size() - numImplicitRefs];
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}
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const MachineOperand& getImplicitOp(unsigned i) const {
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assert(i < numImplicitRefs && "implicit ref# out of range!");
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return operands[i + operands.size() - numImplicitRefs];
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}
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Value* getImplicitRef(unsigned i) {
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return getImplicitOp(i).getVRegValue();
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}
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const Value* getImplicitRef(unsigned i) const {
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return getImplicitOp(i).getVRegValue();
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}
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void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) {
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++numImplicitRefs;
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addRegOperand(V, isDef, isDefAndUse);
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}
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void setImplicitRef(unsigned i, Value* V, bool isDef=false,
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bool isDefAndUse=false) {
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assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
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SetMachineOperandVal(i + getNumOperands(),
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MachineOperand::MO_VirtualRegister,
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V, isDef, isDefAndUse);
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}
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//
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// Information about registers used in this instruction.
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//
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const std::set<int> &getRegsUsed() const {
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return regsUsed;
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}
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bool isRegUsed(int regNum) const {
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return regsUsed.find(regNum) != regsUsed.end();
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}
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// insertusedreg - Add a register to the Used registers set...
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void insertUsedReg(unsigned Reg) {
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regsUsed.insert((int) Reg);
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}
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//
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// Debugging support
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//
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void print(std::ostream &OS, const TargetMachine &TM) const;
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void dump() const;
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friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
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//
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// Define iterators to access the Value operands of the Machine Instruction.
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// Note that these iterators only enumerate the explicit operands.
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// begin() and end() are defined to produce these iterators...
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//
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template<class _MI, class _V> class ValOpIterator;
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typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
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typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
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//===--------------------------------------------------------------------===//
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// Accessors to add operands when building up machine instructions
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//
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/// addRegOperand - Add a MO_VirtualRegister operand to the end of the
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/// operands list...
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///
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void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
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!isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
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}
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void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
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bool isPCRelative = false) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
|
|
operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
|
|
UTy, isPCRelative));
|
|
}
|
|
|
|
void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
|
|
assert(!OperandsComplete() &&
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
|
|
false));
|
|
}
|
|
|
|
|
|
/// addRegOperand - Add a symbolic virtual register reference...
|
|
///
|
|
void addRegOperand(int reg, bool isDef) {
|
|
assert(!OperandsComplete() &&
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
|
|
isDef ? MOTy::Def : MOTy::Use));
|
|
}
|
|
|
|
/// addRegOperand - Add a symbolic virtual register reference...
|
|
///
|
|
void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
|
|
assert(!OperandsComplete() &&
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
|
|
UTy));
|
|
}
|
|
|
|
/// addPCDispOperand - Add a PC relative displacement operand to the MI
|
|
///
|
|
void addPCDispOperand(Value *V) {
|
|
assert(!OperandsComplete() &&
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
|
|
MOTy::Use));
|
|
}
|
|
|
|
/// addMachineRegOperand - Add a virtual register operand to this MachineInstr
|
|
///
|
|
void addMachineRegOperand(int reg, bool isDef) {
|
|
assert(!OperandsComplete() &&
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
|
|
isDef ? MOTy::Def : MOTy::Use));
|
|
insertUsedReg(reg);
|
|
}
|
|
|
|
/// addMachineRegOperand - Add a virtual register operand to this MachineInstr
|
|
///
|
|
void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
|
|
assert(!OperandsComplete() &&
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
|
|
UTy));
|
|
insertUsedReg(reg);
|
|
}
|
|
|
|
/// addZeroExtImmOperand - Add a zero extended constant argument to the
|
|
/// machine instruction.
|
|
///
|
|
void addZeroExtImmOperand(int64_t intValue) {
|
|
assert(!OperandsComplete() &&
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
operands.push_back(MachineOperand(intValue,
|
|
MachineOperand::MO_UnextendedImmed));
|
|
}
|
|
|
|
/// addSignExtImmOperand - Add a zero extended constant argument to the
|
|
/// machine instruction.
|
|
///
|
|
void addSignExtImmOperand(int64_t intValue) {
|
|
assert(!OperandsComplete() &&
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
operands.push_back(MachineOperand(intValue,
|
|
MachineOperand::MO_SignExtendedImmed));
|
|
}
|
|
|
|
void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
|
|
assert(!OperandsComplete() &&
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
operands.push_back(MachineOperand(MBB));
|
|
}
|
|
|
|
/// addFrameIndexOperand - Add an abstract frame index to the instruction
|
|
///
|
|
void addFrameIndexOperand(unsigned Idx) {
|
|
assert(!OperandsComplete() &&
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
|
|
}
|
|
|
|
/// addConstantPoolndexOperand - Add a constant pool object index to the
|
|
/// instruction.
|
|
///
|
|
void addConstantPoolIndexOperand(unsigned I) {
|
|
assert(!OperandsComplete() &&
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
|
|
}
|
|
|
|
void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
|
|
assert(!OperandsComplete() &&
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
operands.push_back(MachineOperand((Value*)GV,
|
|
MachineOperand::MO_GlobalAddress,
|
|
MOTy::Use, isPCRelative));
|
|
}
|
|
|
|
/// addExternalSymbolOperand - Add an external symbol operand to this instr
|
|
///
|
|
void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) {
|
|
operands.push_back(MachineOperand(SymName, isPCRelative));
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Accessors used to modify instructions in place.
|
|
//
|
|
// FIXME: Move this stuff to MachineOperand itself!
|
|
|
|
/// replace - Support to rewrite a machine instruction in place: for now,
|
|
/// simply replace() and then set new operands with Set.*Operand methods
|
|
/// below.
|
|
///
|
|
void replace(int Opcode, unsigned numOperands);
|
|
|
|
/// setOpcode - Replace the opcode of the current instruction with a new one.
|
|
///
|
|
void setOpcode(unsigned Op) { opCode = Op; }
|
|
|
|
/// RemoveOperand - Erase an operand from an instruction, leaving it with one
|
|
/// fewer operand than it started with.
|
|
///
|
|
void RemoveOperand(unsigned i) {
|
|
operands.erase(operands.begin()+i);
|
|
}
|
|
|
|
// Access to set the operands when building the machine instruction
|
|
//
|
|
void SetMachineOperandVal (unsigned i,
|
|
MachineOperand::MachineOperandType operandType,
|
|
Value* V,
|
|
bool isDef=false,
|
|
bool isDefAndUse=false);
|
|
|
|
void SetMachineOperandConst (unsigned i,
|
|
MachineOperand::MachineOperandType operandType,
|
|
int64_t intValue);
|
|
|
|
void SetMachineOperandReg (unsigned i,
|
|
int regNum,
|
|
bool isDef=false);
|
|
|
|
|
|
unsigned substituteValue(const Value* oldVal, Value* newVal,
|
|
bool defsOnly = true);
|
|
|
|
void setOperandHi32(unsigned i) { operands[i].markHi32(); }
|
|
void setOperandLo32(unsigned i) { operands[i].markLo32(); }
|
|
void setOperandHi64(unsigned i) { operands[i].markHi64(); }
|
|
void setOperandLo64(unsigned i) { operands[i].markLo64(); }
|
|
|
|
|
|
// SetRegForOperand -
|
|
// SetRegForImplicitRef -
|
|
// Mark an explicit or implicit operand with its allocated physical register.
|
|
//
|
|
void SetRegForOperand(unsigned i, int regNum);
|
|
void SetRegForImplicitRef(unsigned i, int regNum);
|
|
|
|
//
|
|
// Iterator to enumerate machine operands.
|
|
//
|
|
template<class MITy, class VTy>
|
|
class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
|
|
unsigned i;
|
|
MITy MI;
|
|
|
|
void skipToNextVal() {
|
|
while (i < MI->getNumOperands() &&
|
|
!( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
|
|
MI->getOperand(i).getType() == MachineOperand::MO_CCRegister)
|
|
&& MI->getOperand(i).getVRegValue() != 0))
|
|
++i;
|
|
}
|
|
|
|
inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
|
|
skipToNextVal();
|
|
}
|
|
|
|
public:
|
|
typedef ValOpIterator<MITy, VTy> _Self;
|
|
|
|
inline VTy operator*() const {
|
|
return MI->getOperand(i).getVRegValue();
|
|
}
|
|
|
|
const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
|
|
MachineOperand &getMachineOperand() { return MI->getOperand(i);}
|
|
|
|
inline VTy operator->() const { return operator*(); }
|
|
|
|
inline bool isUseOnly() const { return MI->getOperand(i).opIsUse(); }
|
|
inline bool isDefOnly() const { return MI->getOperand(i).opIsDefOnly(); }
|
|
inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
|
|
|
|
inline _Self& operator++() { i++; skipToNextVal(); return *this; }
|
|
inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
|
|
|
|
inline bool operator==(const _Self &y) const {
|
|
return i == y.i;
|
|
}
|
|
inline bool operator!=(const _Self &y) const {
|
|
return !operator==(y);
|
|
}
|
|
|
|
static _Self begin(MITy MI) {
|
|
return _Self(MI, 0);
|
|
}
|
|
static _Self end(MITy MI) {
|
|
return _Self(MI, MI->getNumOperands());
|
|
}
|
|
};
|
|
|
|
// define begin() and end()
|
|
val_op_iterator begin() { return val_op_iterator::begin(this); }
|
|
val_op_iterator end() { return val_op_iterator::end(this); }
|
|
|
|
const_val_op_iterator begin() const {
|
|
return const_val_op_iterator::begin(this);
|
|
}
|
|
const_val_op_iterator end() const {
|
|
return const_val_op_iterator::end(this);
|
|
}
|
|
};
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Debugging Support
|
|
|
|
std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
|
|
std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
|
|
void PrintMachineInstructions(const Function *F);
|
|
|
|
#endif
|