llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-24 12:29:33 +00:00

History

Matt Arsenault d796cf2e01 Enable (sext x) == C --> x == (trunc C) combine

Extend the existing code which handles this for zext. This makes this
more useful for targets with ZeroOrNegativeOne BooleanContent and
obsoletes a custom combine SI uses for i1 setcc (sext(i1), 0, setne)
since the constant will now be shrunk to i1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224691 91177308-0d34-0410-b5e6-96231b3b80d8

2014-12-21 16:48:42 +00:00

AArch64

IR: Make metadata typeless in assembly

2014-12-15 19:07:53 +00:00

ARM

Add a new string member to the TargetOptions struct for the name

2014-12-18 02:20:58 +00:00

CPP

…

Generic

CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.

2014-12-19 20:50:07 +00:00