llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-04 06:09:05 +00:00

History

Evan Cheng 59ee62d241 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-11 03:57:24 +00:00
..
TargetInfo
Alpha.h
Alpha.td
AlphaAsmPrinter.cpp
AlphaBranchSelector.cpp
AlphaCallingConv.td
AlphaFrameLowering.cpp
AlphaFrameLowering.h
AlphaInstrFormats.td
AlphaInstrInfo.cpp	- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo	2011-07-11 03:57:24 +00:00
AlphaInstrInfo.h	Hide the call to InitMCInstrInfo into tblgen generated ctor.	2011-07-01 17:57:27 +00:00
AlphaInstrInfo.td
AlphaISelDAGToDAG.cpp
AlphaISelLowering.cpp	Add an intrinsic and codegen support for fused multiply-accumulate. The intent	2011-07-08 21:39:21 +00:00
AlphaISelLowering.h
AlphaLLRP.cpp
AlphaMachineFunctionInfo.h
AlphaMCAsmInfo.cpp
AlphaMCAsmInfo.h
AlphaRegisterInfo.cpp
AlphaRegisterInfo.h
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td
AlphaSelectionDAGInfo.cpp
AlphaSelectionDAGInfo.h
AlphaSubtarget.cpp	- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo	2011-07-11 03:57:24 +00:00
AlphaSubtarget.h	Compute feature bits at time of MCSubtargetInfo initialization.	2011-07-07 07:07:08 +00:00
AlphaTargetMachine.cpp	Eliminate asm parser's dependency on TargetMachine:	2011-07-08 01:53:10 +00:00
AlphaTargetMachine.h
CMakeLists.txt	Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.	2011-07-01 22:36:09 +00:00
Makefile	Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.	2011-07-01 22:36:09 +00:00
README.txt

README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum across bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extensions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html