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e6f7c267df
expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This
affects two places in the code: handling cross block values and handling
function return and arguments. Since vectors are already widened by
legalizetypes, this gives us much better code and unblocks x86-64 abi
and SPU abi work.
For example, this (which is a silly example of a cross-block value):
define <4 x float> @test2(<4 x float> %A) nounwind {
%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
%C = fadd <2 x float> %B, %B
br label %BB
BB:
%D = fadd <2 x float> %C, %C
%E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x float> %E
}
Now compiles into:
_test2: ## @test2
## BB#0:
addps %xmm0, %xmm0
addps %xmm0, %xmm0
ret
previously it compiled into:
_test2: ## @test2
## BB#0:
addps %xmm0, %xmm0
pshufd $1, %xmm0, %xmm1
## kill: XMM0<def> XMM0<kill> XMM0<def>
insertps $0, %xmm0, %xmm0
insertps $16, %xmm1, %xmm0
addps %xmm0, %xmm0
ret
This implements rdar://8230384
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112101 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
1.8 KiB
LLVM
71 lines
1.8 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=penryn -asm-verbose=0 -o - | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -mcpu=yonah -march=x86 -asm-verbose=0 -o - | FileCheck %s -check-prefix=X32
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; PR7518
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define void @test1(<2 x float> %Q, float *%P2) nounwind {
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%a = extractelement <2 x float> %Q, i32 0
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%b = extractelement <2 x float> %Q, i32 1
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%c = fadd float %a, %b
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store float %c, float* %P2
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ret void
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; X64: test1:
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; X64-NEXT: pshufd $1, %xmm0, %xmm1
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; X64-NEXT: addss %xmm0, %xmm1
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; X64-NEXT: movss %xmm1, (%rdi)
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; X64-NEXT: ret
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; X32: test1:
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; X32-NEXT: pshufd $1, %xmm0, %xmm1
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; X32-NEXT: addss %xmm0, %xmm1
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; X32-NEXT: movl 4(%esp), %eax
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; X32-NEXT: movss %xmm1, (%eax)
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; X32-NEXT: ret
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}
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define <2 x float> @test2(<2 x float> %Q, <2 x float> %R, <2 x float> *%P) nounwind {
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%Z = fadd <2 x float> %Q, %R
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ret <2 x float> %Z
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; X64: test2:
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; X64-NEXT: addps %xmm1, %xmm0
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; X64-NEXT: ret
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}
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define <2 x float> @test3(<4 x float> %A) nounwind {
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%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
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%C = fadd <2 x float> %B, %B
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ret <2 x float> %C
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; CHECK: test3:
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; CHECK-NEXT: addps %xmm0, %xmm0
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; CHECK-NEXT: ret
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}
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define <2 x float> @test4(<2 x float> %A) nounwind {
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%C = fadd <2 x float> %A, %A
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ret <2 x float> %C
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; CHECK: test4:
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; CHECK-NEXT: addps %xmm0, %xmm0
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; CHECK-NEXT: ret
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}
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define <4 x float> @test5(<4 x float> %A) nounwind {
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%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
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%C = fadd <2 x float> %B, %B
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br label %BB
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BB:
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%D = fadd <2 x float> %C, %C
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%E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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ret <4 x float> %E
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; CHECK: _test5:
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; CHECK-NEXT: addps %xmm0, %xmm0
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; CHECK-NEXT: addps %xmm0, %xmm0
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; CHECK-NEXT: ret
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}
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