Richard Osborne 850f1cd3c0 Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit ...

expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98168 91177308-0d34-0410-b5e6-96231b3b80d8

2010-03-10 18:12:27 +00:00

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Alpha

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ARM

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2010-03-10 03:07:41 +00:00

Blackfin

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CBackend

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CellSPU

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CPP

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Generic

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MBlaze

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Mips

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MSP430

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PIC16

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PowerPC

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2010-03-10 03:07:41 +00:00

SPARC

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Thumb

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2010-03-10 03:07:41 +00:00

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2010-03-10 03:07:41 +00:00

X86

Fix typo.

2010-03-10 07:07:55 +00:00

XCore

Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit

2010-03-10 18:12:27 +00:00