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https://github.com/c64scene-ar/llvm-6502.git
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d80979b25d
The code this patch removes was there to make sure the text sections went before the dwarf sections. That is necessary because MachO uses offsets relative to the start of the file, so adding a section can change relaxations. The dwarf sections were being printed at the start just to produce symbols pointing at the start of those sections. The underlying issue was fixed in r231898. The dwarf sections are now printed when they are about to be used, which is after we printed the text sections. To make sure we don't regress, the patch makes the MachO streamer assert if CodeGen puts anything unexpected after the DWARF sections. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232842 91177308-0d34-0410-b5e6-96231b3b80d8
432 lines
14 KiB
C++
432 lines
14 KiB
C++
//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides ARM specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMBaseInfo.h"
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#include "ARMMCAsmInfo.h"
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#include "ARMMCTargetDesc.h"
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#include "InstPrinter/ARMInstPrinter.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCELFStreamer.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_REGINFO_MC_DESC
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#include "ARMGenRegisterInfo.inc"
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static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
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std::string &Info) {
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if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
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(MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
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(MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
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// Checks for the deprecated CP15ISB encoding:
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// mcr p15, #0, rX, c7, c5, #4
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(MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
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if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
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if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
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Info = "deprecated since v7, use 'isb'";
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return true;
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}
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// Checks for the deprecated CP15DSB encoding:
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// mcr p15, #0, rX, c7, c10, #4
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if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
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Info = "deprecated since v7, use 'dsb'";
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return true;
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}
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}
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// Checks for the deprecated CP15DMB encoding:
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// mcr p15, #0, rX, c7, c10, #5
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if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
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(MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
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Info = "deprecated since v7, use 'dmb'";
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return true;
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}
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}
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return false;
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}
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static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
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std::string &Info) {
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if (STI.getFeatureBits() & llvm::ARM::HasV8Ops && MI.getOperand(1).isImm() &&
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MI.getOperand(1).getImm() != 8) {
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Info = "applying IT instruction to more than one subsequent instruction is "
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"deprecated";
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return true;
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}
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return false;
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}
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static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
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std::string &Info) {
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assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
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"cannot predicate thumb instructions");
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assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
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for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
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assert(MI.getOperand(OI).isReg() && "expected register");
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if (MI.getOperand(OI).getReg() == ARM::SP ||
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MI.getOperand(OI).getReg() == ARM::PC) {
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Info = "use of SP or PC in the list is deprecated";
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return true;
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}
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}
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return false;
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}
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static bool getARMLoadDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
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std::string &Info) {
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assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
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"cannot predicate thumb instructions");
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assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
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bool ListContainsPC = false, ListContainsLR = false;
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for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
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assert(MI.getOperand(OI).isReg() && "expected register");
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switch (MI.getOperand(OI).getReg()) {
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default:
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break;
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case ARM::LR:
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ListContainsLR = true;
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break;
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case ARM::PC:
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ListContainsPC = true;
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break;
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case ARM::SP:
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Info = "use of SP in the list is deprecated";
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return true;
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}
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}
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if (ListContainsPC && ListContainsLR) {
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Info = "use of LR and PC simultaneously in the list is deprecated";
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return true;
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}
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return false;
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}
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#define GET_INSTRINFO_MC_DESC
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#include "ARMGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "ARMGenSubtargetInfo.inc"
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std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
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Triple triple(TT);
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bool isThumb = triple.getArch() == Triple::thumb ||
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triple.getArch() == Triple::thumbeb;
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bool NoCPU = CPU == "generic" || CPU.empty();
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std::string ARMArchFeature;
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switch (triple.getSubArch()) {
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default:
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llvm_unreachable("invalid sub-architecture for ARM");
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case Triple::ARMSubArch_v8:
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if (NoCPU)
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// v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
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// FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
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// FeatureT2XtPk, FeatureCrypto, FeatureCRC
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ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
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"+trustzone,+t2xtpk,+crypto,+crc";
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else
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// Use CPU to figure out the exact features
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ARMArchFeature = "+v8";
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break;
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case Triple::ARMSubArch_v7m:
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isThumb = true;
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if (NoCPU)
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// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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break;
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case Triple::ARMSubArch_v7em:
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if (NoCPU)
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// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
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// FeatureT2XtPk, FeatureMClass
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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break;
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case Triple::ARMSubArch_v7s:
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if (NoCPU)
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// v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
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// Swift
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ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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break;
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case Triple::ARMSubArch_v7:
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// v7 CPUs have lots of different feature sets. If no CPU is specified,
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// then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
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// the "minimum" feature set and use CPU string to figure out the exact
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// features.
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if (NoCPU)
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// v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
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ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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break;
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case Triple::ARMSubArch_v6t2:
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ARMArchFeature = "+v6t2";
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break;
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case Triple::ARMSubArch_v6k:
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ARMArchFeature = "+v6k";
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break;
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case Triple::ARMSubArch_v6m:
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isThumb = true;
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if (NoCPU)
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// v6m: FeatureNoARM, FeatureMClass
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ARMArchFeature = "+v6m,+noarm,+mclass";
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else
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ARMArchFeature = "+v6";
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break;
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case Triple::ARMSubArch_v6:
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ARMArchFeature = "+v6";
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break;
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case Triple::ARMSubArch_v5te:
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ARMArchFeature = "+v5te";
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break;
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case Triple::ARMSubArch_v5:
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ARMArchFeature = "+v5t";
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break;
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case Triple::ARMSubArch_v4t:
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ARMArchFeature = "+v4t";
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break;
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case Triple::NoSubArch:
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break;
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}
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if (isThumb) {
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if (ARMArchFeature.empty())
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ARMArchFeature = "+thumb-mode";
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else
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ARMArchFeature += ",+thumb-mode";
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}
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if (triple.isOSNaCl()) {
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if (ARMArchFeature.empty())
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ARMArchFeature = "+nacl-trap";
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else
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ARMArchFeature += ",+nacl-trap";
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}
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return ARMArchFeature;
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}
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MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS) {
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std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
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if (!FS.empty()) {
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if (!ArchFS.empty())
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ArchFS = ArchFS + "," + FS.str();
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else
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ArchFS = FS;
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}
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MCSubtargetInfo *X = new MCSubtargetInfo();
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InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
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return X;
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}
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static MCInstrInfo *createARMMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitARMMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
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return X;
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}
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static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
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Triple TheTriple(TT);
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MCAsmInfo *MAI;
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if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
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MAI = new ARMMCAsmInfoDarwin(TT);
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else if (TheTriple.isWindowsItaniumEnvironment())
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MAI = new ARMCOFFMCAsmInfoGNU();
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else if (TheTriple.isWindowsMSVCEnvironment())
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MAI = new ARMCOFFMCAsmInfoMicrosoft();
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else
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MAI = new ARMELFMCAsmInfo(TT);
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unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
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MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
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return MAI;
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}
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static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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if (RM == Reloc::Default) {
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Triple TheTriple(TT);
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// Default relocation model on Darwin is PIC, not DynamicNoPIC.
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RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
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}
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X->InitMCCodeGenInfo(RM, CM, OL);
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return X;
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}
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static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
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MCAsmBackend &MAB, raw_ostream &OS,
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MCCodeEmitter *Emitter, bool RelaxAll) {
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return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
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T.getArch() == Triple::thumb);
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}
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static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB,
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raw_ostream &OS,
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MCCodeEmitter *Emitter, bool RelaxAll,
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bool DWARFMustBeAtTheEnd) {
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return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd);
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}
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static MCInstPrinter *createARMMCInstPrinter(const Target &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI) {
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if (SyntaxVariant == 0)
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return new ARMInstPrinter(MAI, MII, MRI, STI);
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return nullptr;
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}
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static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
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MCContext &Ctx) {
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Triple TheTriple(TT);
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if (TheTriple.isOSBinFormatMachO())
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return createARMMachORelocationInfo(Ctx);
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// Default to the stock relocation info.
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return llvm::createMCRelocationInfo(TT, Ctx);
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}
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namespace {
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class ARMMCInstrAnalysis : public MCInstrAnalysis {
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public:
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ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
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bool isUnconditionalBranch(const MCInst &Inst) const override {
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// BCCs with the "always" predicate are unconditional branches.
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if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
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return true;
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return MCInstrAnalysis::isUnconditionalBranch(Inst);
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}
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bool isConditionalBranch(const MCInst &Inst) const override {
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// BCCs with the "always" predicate are unconditional branches.
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if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
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return false;
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return MCInstrAnalysis::isConditionalBranch(Inst);
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}
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bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
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uint64_t Size, uint64_t &Target) const override {
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// We only handle PCRel branches for now.
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if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
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return false;
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int64_t Imm = Inst.getOperand(0).getImm();
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// FIXME: This is not right for thumb.
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Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
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return true;
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}
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};
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}
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static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
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return new ARMMCInstrAnalysis(Info);
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}
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// Force static initialization.
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extern "C" void LLVMInitializeARMTargetMC() {
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for (Target *T : {&TheARMLETarget, &TheARMBETarget, &TheThumbLETarget,
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&TheThumbBETarget}) {
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// Register the MC asm info.
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RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
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// Register the MC codegen info.
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TargetRegistry::RegisterMCCodeGenInfo(*T, createARMMCCodeGenInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(*T,
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ARM_MC::createARMMCSubtargetInfo);
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// Register the MC instruction analyzer.
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TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis);
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TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
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TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer);
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TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer);
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// Register the obj target streamer.
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TargetRegistry::RegisterObjectTargetStreamer(*T,
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createARMObjectTargetStreamer);
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// Register the asm streamer.
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TargetRegistry::RegisterAsmTargetStreamer(*T, createARMTargetAsmStreamer);
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// Register the null TargetStreamer.
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TargetRegistry::RegisterNullTargetStreamer(*T, createARMNullTargetStreamer);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter);
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// Register the MC relocation info.
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TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo);
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}
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// Register the MC Code Emitter
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for (Target *T : {&TheARMLETarget, &TheThumbLETarget})
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TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter);
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for (Target *T : {&TheARMBETarget, &TheThumbBETarget})
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TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter);
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// Register the asm backend.
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TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend);
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TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend);
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TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget,
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createThumbLEAsmBackend);
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TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget,
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createThumbBEAsmBackend);
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}
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