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https://github.com/c64scene-ar/llvm-6502.git
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d811b4bacb
This patch implements LLVM support for the ACLE special register intrinsics in
section 10.1, __arm_{w,r}sr{,p,64}.
This patch is intended to lower the read/write_register instrinsics, used to
implement the special register intrinsics in the clang patch for special
register intrinsics (see http://reviews.llvm.org/D9697), to ARM specific
instructions MRC,MCR,MSR etc. to allow reading an writing of coprocessor
registers in AArch32 and AArch64. This is done by inspecting the register
string passed to the intrinsic and then lowering to the appropriate
instruction.
Patch by Luke Cheeseman.
Differential Revision: http://reviews.llvm.org/D9699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237579 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.1 KiB
LLVM
49 lines
1.1 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-none-eabi -mcpu=cortex-a57 2>&1 | FileCheck %s
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define i64 @read_encoded_register() nounwind {
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entry:
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; CHECK-LABEL: read_encoded_register:
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; CHECK: mrs x0, S1_2_C3_C4_5
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%reg = call i64 @llvm.read_register.i64(metadata !0)
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ret i64 %reg
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}
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define i64 @read_daif() nounwind {
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entry:
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; CHECK-LABEL: read_daif:
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; CHECK: mrs x0, DAIF
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%reg = call i64 @llvm.read_register.i64(metadata !1)
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ret i64 %reg
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}
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define void @write_encoded_register(i64 %x) nounwind {
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entry:
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; CHECK-LABEL: write_encoded_register:
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; CHECK: msr S1_2_C3_C4_5, x0
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call void @llvm.write_register.i64(metadata !0, i64 %x)
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ret void
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}
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define void @write_daif(i64 %x) nounwind {
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entry:
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; CHECK-LABEL: write_daif:
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; CHECK: msr DAIF, x0
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call void @llvm.write_register.i64(metadata !1, i64 %x)
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ret void
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}
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define void @write_daifset() nounwind {
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entry:
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; CHECK-LABEL: write_daifset:
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; CHECK: msr DAIFSET, #2
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call void @llvm.write_register.i64(metadata !2, i64 2)
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ret void
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}
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declare i64 @llvm.read_register.i64(metadata) nounwind
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declare void @llvm.write_register.i64(metadata, i64) nounwind
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!0 = !{!"1:2:3:4:5"}
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!1 = !{!"daif"}
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!2 = !{!"daifset"}
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