mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-29 11:29:39 +00:00
d8149c1bef
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
525 B
LLVM
25 lines
525 B
LLVM
; RUN: llc < %s -march=ptx32 | FileCheck %s
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define ptx_device void @test_bra_direct() {
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; CHECK: bra $L__BB0_1;
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entry:
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br label %loop
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loop:
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br label %loop
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}
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define ptx_device i32 @test_bra_cond_direct(i32 %x, i32 %y) {
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entry:
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; CHECK: setp.le.u32 p0, r[[R0:[0-9]+]], r[[R1:[0-9]+]]
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%p = icmp ugt i32 %x, %y
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; CHECK-NEXT: @p0 bra
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; CHECK-NOT: bra
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br i1 %p, label %clause.if, label %clause.else
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clause.if:
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; CHECK: mov.u32 r{{[0-9]+}}, r[[R0]]
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ret i32 %x
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clause.else:
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; CHECK: mov.u32 r{{[0-9]+}}, r[[R1]]
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ret i32 %y
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}
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