llvm-6502/lib/Target/ARM64
Saleem Abdulrasool d825568843 Target: change member from reference to pointer
This is a preliminary step to help ease the construction of CallLoweringInfo.
Changing the construction to a chained function pattern requires that the
parameter be nullable.  However, rather than copying the vector, save a pointer
rather than the reference to permit a late binding of the arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209080 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-17 21:50:01 +00:00
..
AsmParser [ARM64] Improve diagnostics for Cn operands in SYS instructions 2014-05-15 16:28:32 +00:00
Disassembler [ARM64] Parse fixed vector lanes properly so that diagnostics can be emitted 2014-05-15 11:07:57 +00:00
InstPrinter TableGen: fix operand counting for aliases 2014-05-16 09:42:04 +00:00
MCTargetDesc [ARM64-BE] Fix byte order of CIE and FDE frames for exception handling 2014-05-14 16:51:58 +00:00
TargetInfo
Utils
ARM64.h
ARM64.td
ARM64AddressTypePromotion.cpp
ARM64AdvSIMDScalarPass.cpp
ARM64AsmPrinter.cpp
ARM64BranchRelaxation.cpp
ARM64CallingConv.h
ARM64CallingConvention.td
ARM64CleanupLocalDynamicTLSPass.cpp
ARM64CollectLOH.cpp
ARM64ConditionalCompares.cpp
ARM64DeadRegisterDefinitionsPass.cpp
ARM64ExpandPseudoInsts.cpp
ARM64FastISel.cpp Delete getAliasedGlobal. 2014-05-16 22:37:03 +00:00
ARM64FrameLowering.cpp [ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out argument stack from callee. 2014-05-15 01:33:17 +00:00
ARM64FrameLowering.h
ARM64InstrAtomics.td
ARM64InstrFormats.td [ARM64] Increases the Sched Model accuracy for Cortex-A53. 2014-05-16 17:15:33 +00:00
ARM64InstrInfo.cpp [ARM64] Increases the Sched Model accuracy for Cortex-A53. 2014-05-16 17:15:33 +00:00
ARM64InstrInfo.h [ARM64] Increases the Sched Model accuracy for Cortex-A53. 2014-05-16 17:15:33 +00:00
ARM64InstrInfo.td ARM64: disable printing of swapped compare-mask aliases 2014-05-16 09:41:16 +00:00
ARM64ISelDAGToDAG.cpp [ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R. 2014-05-16 09:39:02 +00:00
ARM64ISelLowering.cpp Target: change member from reference to pointer 2014-05-17 21:50:01 +00:00
ARM64ISelLowering.h Revert "Implement global merge optimization for global variables." 2014-05-16 13:02:18 +00:00
ARM64LoadStoreOptimizer.cpp [ARM64] Fix wrong comment in load/store optimization pass. 2014-05-16 16:50:13 +00:00
ARM64MachineFunctionInfo.h [ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out argument stack from callee. 2014-05-15 01:33:17 +00:00
ARM64MCInstLower.cpp
ARM64MCInstLower.h
ARM64PerfectShuffle.h
ARM64PromoteConstant.cpp
ARM64RegisterInfo.cpp
ARM64RegisterInfo.h
ARM64RegisterInfo.td ARM64: add correct vector registers during asm parsing 2014-05-15 11:16:19 +00:00
ARM64SchedA53.td [ARM64] Increases the Sched Model accuracy for Cortex-A53. 2014-05-16 17:15:33 +00:00
ARM64SchedCyclone.td [ARM64] Increases the Sched Model accuracy for Cortex-A53. 2014-05-16 17:15:33 +00:00
ARM64Schedule.td [ARM64] Increases the Sched Model accuracy for Cortex-A53. 2014-05-16 17:15:33 +00:00
ARM64SelectionDAGInfo.cpp
ARM64SelectionDAGInfo.h
ARM64StorePairSuppress.cpp
ARM64Subtarget.cpp
ARM64Subtarget.h
ARM64TargetMachine.cpp
ARM64TargetMachine.h
ARM64TargetObjectFile.cpp
ARM64TargetObjectFile.h
ARM64TargetTransformInfo.cpp
CMakeLists.txt
LLVMBuild.txt Fix broken build 2014-05-09 18:06:22 +00:00
Makefile