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https://github.com/c64scene-ar/llvm-6502.git
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8239daf7c8
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
2.0 KiB
LLVM
60 lines
2.0 KiB
LLVM
; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s
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; rdar://8598427
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; Adjust if-converter heuristics to avoid predicating vmrs which can cause
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; significant regression.
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%struct.xyz_t = type { double, double, double }
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define i32 @effie(i32 %tsets, %struct.xyz_t* nocapture %p, i32 %a, i32 %b, i32 %c) nounwind readonly noinline {
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; CHECK: effie:
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entry:
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%0 = icmp sgt i32 %tsets, 0
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br i1 %0, label %bb.nph, label %bb6
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bb.nph: ; preds = %entry
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%1 = add nsw i32 %b, %a
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%2 = add nsw i32 %1, %c
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br label %bb
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bb: ; preds = %bb4, %bb.nph
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; CHECK: vcmpe.f64
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; CHECK: vmrs apsr_nzcv, fpscr
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%r.19 = phi i32 [ 0, %bb.nph ], [ %r.0, %bb4 ]
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%n.08 = phi i32 [ 0, %bb.nph ], [ %10, %bb4 ]
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%scevgep10 = getelementptr inbounds %struct.xyz_t* %p, i32 %n.08, i32 0
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%scevgep11 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 1
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%3 = load double* %scevgep10, align 4
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%4 = load double* %scevgep11, align 4
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%5 = fcmp uge double %3, %4
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br i1 %5, label %bb3, label %bb1
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bb1: ; preds = %bb
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; CHECK-NOT: it
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; CHECK-NOT: vcmpemi
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; CHECK-NOT: vmrsmi
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; CHECK: vcmpe.f64
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; CHECK: vmrs apsr_nzcv, fpscr
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%scevgep12 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 2
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%6 = load double* %scevgep12, align 4
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%7 = fcmp uge double %3, %6
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br i1 %7, label %bb3, label %bb2
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bb2: ; preds = %bb1
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%8 = add nsw i32 %2, %r.19
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br label %bb4
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bb3: ; preds = %bb1, %bb
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%9 = add nsw i32 %r.19, 1
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br label %bb4
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bb4: ; preds = %bb3, %bb2
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%r.0 = phi i32 [ %9, %bb3 ], [ %8, %bb2 ]
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%10 = add nsw i32 %n.08, 1
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%exitcond = icmp eq i32 %10, %tsets
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br i1 %exitcond, label %bb6, label %bb
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bb6: ; preds = %bb4, %entry
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%r.1.lcssa = phi i32 [ 0, %entry ], [ %r.0, %bb4 ]
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ret i32 %r.1.lcssa
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}
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