Moritz Roth d84561bf69 ARM: Fix and re-enable load/store optimizer for Thumb1. ... In a previous iteration of the pass, we would try to compensate for writeback by updating later instructions and/or inserting a SUBS to reset the base register if necessary. Since such a SUBS sets the condition flags it's not generally safe to do this. For now, only merge LDR/STRs if there is no writeback to the base register (LDM that loads into the base register) or the base register is killed by one of the merged instructions. These cases are clear wins both in terms of instruction count and performance. Also add three new test cases, and update the existing ones accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215729 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-15 17:00:30 +00:00
..
AArch64	[AArch64] Narrow arguments passed in wrong position on the stack in	2014-08-15 14:29:57 +00:00
ARM	[FastISel][ARM] Fall-back to constant pool loads when materializing an i32 constant.	2014-08-14 23:29:49 +00:00
CPP
Generic	Use "weak alias" instead of "alias weak"	2014-07-30 22:51:54 +00:00
Hexagon	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
Inputs
Mips	[mips] Improve robustness of some tests.	2014-08-14 13:10:48 +00:00
MSP430
NVPTX	[NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types	2014-07-23 20:23:49 +00:00
PowerPC	[PPC64] Add test case for r215685.	2014-08-15 13:51:57 +00:00
R600	R600: Correctly set the src value offset for scalarized kernel args	2014-08-13 18:14:11 +00:00
SPARC
SystemZ
Thumb	ARM: Fix and re-enable load/store optimizer for Thumb1.	2014-08-15 17:00:30 +00:00
Thumb2	ARM: do not generate BLX instructions on Cortex-M CPUs.	2014-08-06 11:13:14 +00:00
X86	[x86] Add the initial skeleton of type-based dispatch for AVX vectors in	2014-08-15 11:01:40 +00:00
XCore	llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.	2014-07-04 11:58:03 +00:00