llvm-6502/test/MC/PowerPC/ppc64-relocs-01.ll
Rafael Espindola 7486d92a6c Change how we iterate over relocations on ELF.
For COFF and MachO, sections semantically have relocations that apply to them.
That is not the case on ELF.

In relocatable objects (.o), a section with relocations in ELF has offsets to
another section where the relocations should be applied.

In dynamic objects and executables, relocations don't have an offset, they have
a virtual address. The section sh_info may or may not point to another section,
but that is not actually used for resolving the relocations.

This patch exposes that in the ObjectFile API. It has the following advantages:

* Most (all?) clients can handle this more efficiently. They will normally walk
all relocations, so doing an effort to iterate in a particular order doesn't
save time.

* llvm-readobj now prints relocations in the same way the native readelf does.

* probably most important, relocations that don't point to any section are now
visible. This is the case of relocations in the rela.dyn section. See the
updated relocation-executable.test for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182908 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-30 03:05:14 +00:00

50 lines
1.6 KiB
LLVM

;; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -O3 -code-model=small \
;; RUN: -filetype=obj %s -o - | \
;; RUN: llvm-readobj -r | FileCheck %s
;; FIXME: this file need to be in .s form, change when asm parse is done.
@number64 = global i64 10, align 8
define i64 @access_int64(i64 %a) nounwind readonly {
entry:
%0 = load i64* @number64, align 8
%cmp = icmp eq i64 %0, %a
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
declare double @sin(double) nounwind
define double @test_branch24 (double %x) nounwind readonly {
entry:
%add = call double @sin(double %x) nounwind
ret double %add
}
;; CHECK: Relocations [
;; The relocations in .rela.text are the 'number64' load using a
;; R_PPC64_TOC16_DS against the .toc and the 'sin' external function
;; address using a R_PPC64_REL24
;; CHECK: Section ({{[0-9]+}}) .rela.text {
;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_DS .toc
;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_REL24 sin
;; CHECK-NEXT: }
;; The .opd entry for the 'access_int64' function creates 2 relocations:
;; 1. A R_PPC64_ADDR64 against the .text segment plus addend (the function
; address itself);
;; 2. And a R_PPC64_TOC against no symbol (the linker will replace for the
;; module's TOC base).
;; CHECK: Section ({{[0-9]+}}) .rela.opd {
;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_ADDR64 .text 0x0
;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC - 0x0
;; Finally the TOC creates the relocation for the 'number64'.
;; CHECK: Section ({{[0-9]+}}) .rela.toc {
;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_ADDR64 number64 0x0
;; CHECK-NEXT: }
;; CHECK-NEXT: ]