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602b0c8c17
naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
615 lines
23 KiB
C++
615 lines
23 KiB
C++
//===- BlackfinISelLowering.cpp - Blackfin DAG Lowering Implementation ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the interfaces that Blackfin uses to lower LLVM code
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// into a selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#include "BlackfinISelLowering.h"
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#include "BlackfinTargetMachine.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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#include "BlackfinGenCallingConv.inc"
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//===----------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===----------------------------------------------------------------------===//
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BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
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: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
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setShiftAmountType(MVT::i16);
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setBooleanContents(ZeroOrOneBooleanContent);
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setStackPointerRegisterToSaveRestore(BF::SP);
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setIntDivIsCheap(false);
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// Set up the legal register classes.
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addRegisterClass(MVT::i32, BF::DRegisterClass);
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addRegisterClass(MVT::i16, BF::D16RegisterClass);
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computeRegisterProperties();
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// Blackfin doesn't have i1 loads or stores
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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// i16 registers don't do much
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setOperationAction(ISD::AND, MVT::i16, Promote);
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setOperationAction(ISD::OR, MVT::i16, Promote);
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setOperationAction(ISD::XOR, MVT::i16, Promote);
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setOperationAction(ISD::CTPOP, MVT::i16, Promote);
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// The expansion of CTLZ/CTTZ uses AND/OR, so we might as well promote
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// immediately.
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setOperationAction(ISD::CTLZ, MVT::i16, Promote);
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setOperationAction(ISD::CTTZ, MVT::i16, Promote);
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setOperationAction(ISD::SETCC, MVT::i16, Promote);
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// Blackfin has no division
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setOperationAction(ISD::SDIV, MVT::i16, Expand);
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setOperationAction(ISD::SDIV, MVT::i32, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i16, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UDIV, MVT::i16, Expand);
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setOperationAction(ISD::UDIV, MVT::i32, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i16, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::MULHU, MVT::i32, Expand);
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setOperationAction(ISD::MULHS, MVT::i32, Expand);
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// No carry-in operations.
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setOperationAction(ISD::ADDE, MVT::i32, Custom);
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setOperationAction(ISD::SUBE, MVT::i32, Custom);
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// Blackfin has no intrinsics for these particular operations.
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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// i32 has native CTPOP, but not CTLZ/CTTZ
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setOperationAction(ISD::CTLZ, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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// READCYCLECOUNTER needs special type legalization.
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setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
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// We don't have line number support yet.
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setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
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setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
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// Use the default implementation.
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setOperationAction(ISD::VACOPY, MVT::Other, Expand);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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}
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const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case BFISD::CALL: return "BFISD::CALL";
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case BFISD::RET_FLAG: return "BFISD::RET_FLAG";
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case BFISD::Wrapper: return "BFISD::Wrapper";
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}
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}
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MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
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// SETCC always sets the CC register. Technically that is an i1 register, but
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// that type is not legal, so we treat it as an i32 register.
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return MVT::i32;
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}
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SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
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SelectionDAG &DAG) {
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DebugLoc DL = Op.getDebugLoc();
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GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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Op = DAG.getTargetGlobalAddress(GV, MVT::i32);
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return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
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}
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SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
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DebugLoc DL = Op.getDebugLoc();
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int JTI = cast<JumpTableSDNode>(Op)->getIndex();
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Op = DAG.getTargetJumpTable(JTI, MVT::i32);
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return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
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}
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SDValue
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BlackfinTargetLowering::LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg>
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&Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
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ArgLocs, *DAG.getContext());
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CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space
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CCInfo.AnalyzeFormalArguments(Ins, CC_Blackfin);
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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if (VA.isRegLoc()) {
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EVT RegVT = VA.getLocVT();
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TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
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BF::PRegisterClass : BF::DRegisterClass;
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assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
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assert(RC->hasType(RegVT) && "Unexpected regclass in CCState");
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unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
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MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
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SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
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// If this is an 8 or 16-bit value, it is really passed promoted to 32
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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// right size.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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if (VA.getLocInfo() != CCValAssign::Full)
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ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
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InVals.push_back(ArgValue);
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} else {
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assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
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unsigned ObjSize = VA.getLocVT().getStoreSize();
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int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
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SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
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InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
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}
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}
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return Chain;
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}
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SDValue
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BlackfinTargetLowering::LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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DebugLoc dl, SelectionDAG &DAG) {
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// CCValAssign - represent the assignment of the return value to locations.
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SmallVector<CCValAssign, 16> RVLocs;
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// CCState - Info about the registers and stack slot.
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CCState CCInfo(CallConv, isVarArg, DAG.getTarget(),
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RVLocs, *DAG.getContext());
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// Analize return values.
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CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin);
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// If this is the first return lowered for this function, add the regs to the
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// liveout set for the function.
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if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
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for (unsigned i = 0; i != RVLocs.size(); ++i)
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DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
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}
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SDValue Flag;
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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SDValue Opi = Outs[i].Val;
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// Expand to i32 if necessary
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switch (VA.getLocInfo()) {
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default: llvm_unreachable("Unknown loc info!");
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi);
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break;
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case CCValAssign::ZExt:
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Opi = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Opi);
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break;
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case CCValAssign::AExt:
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Opi = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Opi);
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break;
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}
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Opi, SDValue());
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// Guarantee that all emitted copies are stuck together with flags.
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Flag = Chain.getValue(1);
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}
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if (Flag.getNode()) {
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return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
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} else {
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return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain);
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}
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}
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SDValue
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BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) {
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs,
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*DAG.getContext());
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CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space
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CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin);
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// Get the size of the outgoing arguments stack space requirement.
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unsigned ArgsSize = CCInfo.getNextStackOffset();
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
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SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
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SmallVector<SDValue, 8> MemOpChains;
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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SDValue Arg = Outs[i].Val;
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default: llvm_unreachable("Unknown loc info!");
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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}
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// Arguments that can be passed on register must be kept at
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// RegsToPass vector
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if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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} else {
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assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
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int Offset = VA.getLocMemOffset();
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assert(Offset%4 == 0 && "Unaligned LocMemOffset");
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assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type");
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SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32);
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SDValue OffsetN = DAG.getIntPtrConstant(Offset);
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OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN);
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MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, OffsetN,
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PseudoSourceValue::getStack(),
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Offset));
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}
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}
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// Transform all store nodes into one single node because
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// all store nodes are independent of each other.
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of copy-to-reg nodes chained together with token
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// chain and flag operands which copy the outgoing args into registers.
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// The InFlag in necessary since all emited instructions must be
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// stuck together.
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SDValue InFlag;
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
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RegsToPass[i].second, InFlag);
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InFlag = Chain.getValue(1);
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}
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// If the callee is a GlobalAddress node (quite common, every direct call is)
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// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
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// Likewise ExternalSymbol -> TargetExternalSymbol.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
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else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
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Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
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std::vector<EVT> NodeTys;
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NodeTys.push_back(MVT::Other); // Returns a chain
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NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
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SDValue Ops[] = { Chain, Callee, InFlag };
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Chain = DAG.getNode(BFISD::CALL, dl, NodeTys, Ops,
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InFlag.getNode() ? 3 : 2);
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InFlag = Chain.getValue(1);
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Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
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DAG.getIntPtrConstant(0, true), InFlag);
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InFlag = Chain.getValue(1);
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// Assign locations to each value returned by this call.
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SmallVector<CCValAssign, 16> RVLocs;
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CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs,
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*DAG.getContext());
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RVInfo.AnalyzeCallResult(Ins, RetCC_Blackfin);
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// Copy all of the result registers out of their specified physreg.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &RV = RVLocs[i];
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unsigned Reg = RV.getLocReg();
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Chain = DAG.getCopyFromReg(Chain, dl, Reg,
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RVLocs[i].getLocVT(), InFlag);
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SDValue Val = Chain.getValue(0);
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InFlag = Chain.getValue(2);
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Chain = Chain.getValue(1);
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// Callee is responsible for extending any i16 return values.
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switch (RV.getLocInfo()) {
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case CCValAssign::SExt:
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Val = DAG.getNode(ISD::AssertSext, dl, RV.getLocVT(), Val,
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DAG.getValueType(RV.getValVT()));
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break;
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case CCValAssign::ZExt:
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Val = DAG.getNode(ISD::AssertZext, dl, RV.getLocVT(), Val,
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DAG.getValueType(RV.getValVT()));
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break;
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default:
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break;
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}
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// Truncate to valtype
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if (RV.getLocInfo() != CCValAssign::Full)
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Val = DAG.getNode(ISD::TRUNCATE, dl, RV.getValVT(), Val);
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InVals.push_back(Val);
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}
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return Chain;
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}
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// Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
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// add-with-carry instructions.
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SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) {
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// Operands: lhs, rhs, carry-in (AC0 flag)
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// Results: sum, carry-out (AC0 flag)
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DebugLoc dl = Op.getDebugLoc();
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unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
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|
// zext incoming carry flag in AC0 to 32 bits
|
|
SDNode* CarryIn = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
|
|
/* flag= */ Op.getOperand(2));
|
|
CarryIn = DAG.getMachineNode(BF::MOVECC_zext, dl, MVT::i32,
|
|
SDValue(CarryIn, 0));
|
|
|
|
// Add operands, produce sum and carry flag
|
|
SDNode *Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Flag,
|
|
Op.getOperand(0), Op.getOperand(1));
|
|
|
|
// Store intermediate carry from Sum
|
|
SDNode* Carry1 = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
|
|
/* flag= */ SDValue(Sum, 1));
|
|
|
|
// Add incoming carry, again producing an output flag
|
|
Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Flag,
|
|
SDValue(Sum, 0), SDValue(CarryIn, 0));
|
|
|
|
// Update AC0 with the intermediate carry, producing a flag.
|
|
SDNode *CarryOut = DAG.getMachineNode(BF::OR_ac0_cc, dl, MVT::Flag,
|
|
SDValue(Carry1, 0));
|
|
|
|
// Compose (i32, flag) pair
|
|
SDValue ops[2] = { SDValue(Sum, 0), SDValue(CarryOut, 0) };
|
|
return DAG.getMergeValues(ops, 2, dl);
|
|
}
|
|
|
|
SDValue BlackfinTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
|
|
switch (Op.getOpcode()) {
|
|
default:
|
|
Op.getNode()->dump();
|
|
llvm_unreachable("Should not custom lower this!");
|
|
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
|
|
case ISD::GlobalTLSAddress:
|
|
llvm_unreachable("TLS not implemented for Blackfin.");
|
|
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
|
|
// Frame & Return address. Currently unimplemented
|
|
case ISD::FRAMEADDR: return SDValue();
|
|
case ISD::RETURNADDR: return SDValue();
|
|
case ISD::ADDE:
|
|
case ISD::SUBE: return LowerADDE(Op, DAG);
|
|
}
|
|
}
|
|
|
|
void
|
|
BlackfinTargetLowering::ReplaceNodeResults(SDNode *N,
|
|
SmallVectorImpl<SDValue> &Results,
|
|
SelectionDAG &DAG) {
|
|
DebugLoc dl = N->getDebugLoc();
|
|
switch (N->getOpcode()) {
|
|
default:
|
|
llvm_unreachable("Do not know how to custom type legalize this operation!");
|
|
return;
|
|
case ISD::READCYCLECOUNTER: {
|
|
// The low part of the cycle counter is in CYCLES, the high part in
|
|
// CYCLES2. Reading CYCLES will latch the value of CYCLES2, so we must read
|
|
// CYCLES2 last.
|
|
SDValue TheChain = N->getOperand(0);
|
|
SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, MVT::i32);
|
|
SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, MVT::i32);
|
|
// Use a buildpair to merge the two 32-bit values into a 64-bit one.
|
|
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, lo, hi));
|
|
// Outgoing chain. If we were to use the chain from lo instead, it would be
|
|
// possible to entirely eliminate the CYCLES2 read in (i32 (trunc
|
|
// readcyclecounter)). Unfortunately this could possibly delay the CYCLES2
|
|
// read beyond the next CYCLES read, leading to invalid results.
|
|
Results.push_back(hi.getValue(1));
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// getFunctionAlignment - Return the Log2 alignment of this function.
|
|
unsigned BlackfinTargetLowering::getFunctionAlignment(const Function *F) const {
|
|
return 2;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Blackfin Inline Assembly Support
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// getConstraintType - Given a constraint letter, return the type of
|
|
/// constraint it is for this target.
|
|
BlackfinTargetLowering::ConstraintType
|
|
BlackfinTargetLowering::getConstraintType(const std::string &Constraint) const {
|
|
if (Constraint.size() != 1)
|
|
return TargetLowering::getConstraintType(Constraint);
|
|
|
|
switch (Constraint[0]) {
|
|
// Standard constraints
|
|
case 'r':
|
|
return C_RegisterClass;
|
|
|
|
// Blackfin-specific constraints
|
|
case 'a':
|
|
case 'd':
|
|
case 'z':
|
|
case 'D':
|
|
case 'W':
|
|
case 'e':
|
|
case 'b':
|
|
case 'v':
|
|
case 'f':
|
|
case 'c':
|
|
case 't':
|
|
case 'u':
|
|
case 'k':
|
|
case 'x':
|
|
case 'y':
|
|
case 'w':
|
|
return C_RegisterClass;
|
|
case 'A':
|
|
case 'B':
|
|
case 'C':
|
|
case 'Z':
|
|
case 'Y':
|
|
return C_Register;
|
|
}
|
|
|
|
// Not implemented: q0-q7, qA. Use {R2} etc instead
|
|
|
|
return TargetLowering::getConstraintType(Constraint);
|
|
}
|
|
|
|
/// getRegForInlineAsmConstraint - Return register no and class for a C_Register
|
|
/// constraint.
|
|
std::pair<unsigned, const TargetRegisterClass*> BlackfinTargetLowering::
|
|
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
|
|
typedef std::pair<unsigned, const TargetRegisterClass*> Pair;
|
|
using namespace BF;
|
|
|
|
if (Constraint.size() != 1)
|
|
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
|
|
|
switch (Constraint[0]) {
|
|
// Standard constraints
|
|
case 'r':
|
|
return Pair(0U, VT == MVT::i16 ? D16RegisterClass : DPRegisterClass);
|
|
|
|
// Blackfin-specific constraints
|
|
case 'a': return Pair(0U, PRegisterClass);
|
|
case 'd': return Pair(0U, DRegisterClass);
|
|
case 'e': return Pair(0U, AccuRegisterClass);
|
|
case 'A': return Pair(A0, AccuRegisterClass);
|
|
case 'B': return Pair(A1, AccuRegisterClass);
|
|
case 'b': return Pair(0U, IRegisterClass);
|
|
case 'v': return Pair(0U, BRegisterClass);
|
|
case 'f': return Pair(0U, MRegisterClass);
|
|
case 'C': return Pair(CC, JustCCRegisterClass);
|
|
case 'x': return Pair(0U, GRRegisterClass);
|
|
case 'w': return Pair(0U, ALLRegisterClass);
|
|
case 'Z': return Pair(P3, PRegisterClass);
|
|
case 'Y': return Pair(P1, PRegisterClass);
|
|
}
|
|
|
|
// Not implemented: q0-q7, qA. Use {R2} etc instead.
|
|
// Constraints z, D, W, c, t, u, k, and y use non-existing classes, defer to
|
|
// getRegClassForInlineAsmConstraint()
|
|
|
|
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
|
}
|
|
|
|
std::vector<unsigned> BlackfinTargetLowering::
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
|
|
using namespace BF;
|
|
|
|
if (Constraint.size() != 1)
|
|
return std::vector<unsigned>();
|
|
|
|
switch (Constraint[0]) {
|
|
case 'z': return make_vector<unsigned>(P0, P1, P2, 0);
|
|
case 'D': return make_vector<unsigned>(R0, R2, R4, R6, 0);
|
|
case 'W': return make_vector<unsigned>(R1, R3, R5, R7, 0);
|
|
case 'c': return make_vector<unsigned>(I0, I1, I2, I3,
|
|
B0, B1, B2, B3,
|
|
L0, L1, L2, L3, 0);
|
|
case 't': return make_vector<unsigned>(LT0, LT1, 0);
|
|
case 'u': return make_vector<unsigned>(LB0, LB1, 0);
|
|
case 'k': return make_vector<unsigned>(LC0, LC1, 0);
|
|
case 'y': return make_vector<unsigned>(RETS, RETN, RETI, RETX, RETE,
|
|
ASTAT, SEQSTAT, USP, 0);
|
|
}
|
|
|
|
return std::vector<unsigned>();
|
|
}
|
|
|
|
bool BlackfinTargetLowering::
|
|
isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
|
|
// The Blackfin target isn't yet aware of offsets.
|
|
return false;
|
|
}
|