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3be03406c9
Module*. Also, dropped uses of TargetMachine where unnecessary. The only target which still takes a TargetMachine& is Mips, I would appreciate it if someone would normalize this to match other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
28 lines
822 B
C++
28 lines
822 B
C++
//===- XCoreSubtarget.cpp - XCore Subtarget Information -----------*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the XCore specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "XCoreSubtarget.h"
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#include "XCore.h"
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#include "XCoreGenSubtarget.inc"
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using namespace llvm;
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XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &FS)
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: IsXS1A(false),
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IsXS1B(false)
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{
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std::string CPU = "xs1a-generic";
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// Parse features string.
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ParseSubtargetFeatures(FS, CPU);
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}
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